I have a net tie that connects two ground planes. However, because of the pad clearance, the copper pour goes around the pads and causes gaps as shown in the image. I initially thought that setting the pad with negative clearance would solve this issue but it won’t let me set that. How do I do this and also is this recommended?
I am not sure what I am looking at in your screen shot; I feel like it could benefit from some arrows and labels. You mention ground planes but the red looks like odd shaped traces around a couple of round pads.
But: I had what may be a similar issue. The solution was: Make sure that the keyword field in your net tie footprint says “net tie” at the beginning.
The red part is a fill on the F.Cu layer. The blue is B.Cu. GND and GNDA are two copper pours.
Maybe I am the only one, but I still do not understand the image. Where is the net tie?
It’s the small strip that connects the two blue planes. One side is marked GNDA and the other is GND. Essentially its connecting the GNDA and GND planes at a single point on the B.Cu layer. Here is what it looks like on the B.Cu side.
Can you attach the pcb file here, or strip off everything except the relevant items and attach it here? Or create a new self-standing example file?
Same here. I see two via’s or THT pads, but don’t know what they are or how they’re used.
I also do not see two different copper zones for:
I’m guessing it’s a 4 layer PCB and the other layers are not shown.
So follow eeliks advice. Zip up a simplified version of your project and post it here.
In a more general sense the use of separate GND planes for digital and analog GND is deprecated, and often it’s better to use a single big GND zone for the whole PCB in combination with attention of how the currents flow through the GND plane.
Thank you. That suggests that I am not stupid.
I suspect (as with so many other things) that the numbers matter. So there may be a difference between a buck controller chip regulating 1 Amp and one regulating 30 Amps. Thinking about how the currents flow is probably valid but that requires a bit more judgement.
Edit the footprint for the net tie (probably just the local instance in pcbnew using the right click menu) and set “Pad connection to zones” to “solid”.
From a quick experiment it looks like that does what you appear to want.