Hello team, haven’t posted in a while because I’ve been reasonably successful making things complicated for myself, hence this topic. I’ve attached the pcbnew and eeschema files but I don’t know if anything else should go with them (like the libraries) to make them intelligible.
This design is for a voltage-controlled envelope generator (in the analog synth domain). I’ve somewhat arbitrarily constrained myself to a specific board size but I could expand it (in the Y direction). I’ve previously done three iterations of a “conventional” EG/ADSR controlled by pots and took a bit of a leap to the current design. But the specifics of the circuit are not really of the point.
Where I am now is that it doesn’t look to me like I can finish laying out the traces without a whole lot of vias, so I’m stopping to fish for some advice. Any kind of commentary is welcome.
The general design is that jacks, LEDs and pots go on the front, and JLCPCB will fab the components on the bottom. I think looking at the ratsnest should give a sufficient idea where I am. My questions:
- Is the design complex enough that it would be reasonable to go to a 4-layer board? Are there any particular pitfalls to consider? I would do a layer for ground, one for (most of the) power traces and the remaining two should leave plenty of elbow room for the functional traces.
- Are there any glaring missteps visible in what I’ve go so far?
- Am I worried too much about adding vias? Sometimes I think I take it as too much of a challenge to minimize them and end up with tortuously-routed traces. (So far I have no (conclusive) evidence anything I’ve done has been detrimental to any circuit behaviour (which operates in the DC-to-10KHz domain)).
- Should I be thinking of some other approach? I have one good design for a voltage-controlled amplifier that used separate boards for controls and internals but that was one of my last THT designs so routing wasn’t a challenge.
“Thanks for any insight you can provide.”