Hi all, new KiCAD user here though I’m familiar with CAD packages “E” and “A”.
I recently sent a board that I had designed with KiCAD 5.1.4/Windows to a low-cost board house. The board was DRC checked with the default 0.3mm minimum drill size. The board house kicked back the design because the SO-8EP footprint in it had thermal vias using a 0.2mm drill. In the footprint, those vias are made as through-hole pads with a 0.2mm drill (I’m presuming the small size is to minimize solder thieving).
So the question is, does DRC check the drill sizes on footprint pads, or does it only check via drill sizes? Or is there an option I need to turn on to get pad drills to be checked properly?
Steps to re-create:
1.) Create a test project. Open the pcb, draw a board outline.
2.) Place a footprint- Package_SO: SOIC-8-1EP_3.9x4.9mm_P1.27mm_EP2.29x3mm_ThermalVias
3.) Check that Board Setup / Design Rules / Minimum Via Drill is set to 0.3mm
4.) Note that the thermal vias on the footprint are 0.2mm
5.) Run DRC. No errors are reported.
6.) Place a via on the board with a drill diameter of 0.2mm
7.) Run DRC again. An error for “Via Drill too small” is noted.
Thanks for filing the bug. But I couldn’t get the example you filed in the bug-report to fail as you say. When I opened your test, the design rules were set for a minimum via size of 0.4mm, and a minimum via drill of 0.3mm. Thus, no error when checking your vias of 0.6/0.3.
In the example I posted above, I suspect there’s some sort of issue related to the fact that the thermal vias are actually through-hole pads, not vias. It’s almost like the DRC dialog is literally correct- that only via drill sizes are checked.
Experimentation shows that this is actually pad size and that minimum via drill is set at 0.3mm somewhere else, any ideas where?
Edit - found it in Design Rules one level above the DRC check.
So the OPs problem is that the 0.2mm hole in the EP is not being treated as a via. The problem is tha a uVia is laser drilled and EPs are mechanically drilled, so should use the Via limit
Thermal vias in a generic footprint are problematic anyways. The needs depend so much on the actual component and application. You should probably copy the footprint to your own library and modify it anyways.
This could be seen as a bug in the footprint, too. 0.2mm is usually more expensive than 0.3mm, the latter seems to be the lower limit with many manufacturers. But with 0.3mm there would be the paste problem.
Many times I have thought that footprints could have optional features, like with or without thermal vias or even several different sets of thermal vias. That would also make the library and searching and browsing through the library leaner and easier.