The DIP-nn footprints and 3D models are apparently script-generated and increase monotonically in size.
Reality is however different, DIP-14 and DIP-16 packages have almost identical size. See for example
Bottom line is, that the DIP-14 courtyards are too small. The footprint has a 18.4 mm courtyard, while in reality packages are 19.5 mm (in some specs even up to 20.0 mm).
I’m new to kicad, and really wonder, why footprints for such a legacy part show such a discrepancy.
Because they’re exactly that, legacy parts. They don’t get much use, and probably the same people who care about accurate courtyards - the ones doing actual design for manufacture, typically, in a commercial context - are not the ones using a lot of DIPs. Courtyards are a new feature and these footprints probably predate them, with courtyards added later.
You could probably open an issue on the library repository to discuss changing the DIP courtyard dimensions
Yes I would bet that there are relatively few new designs using DIPs in mass production. I know of no advantage relative to SOIC for example. I use some DIPs in home projects because I have the parts and/or I want to hand wire them without a pcb.
I would raise an issue on this, it’s still an error and people do use KiCad to make replacement PCBs for old equipment where a PCB battery has leaked.(Quad FM4 tuner is famous for this)
Probably nobody notices any problem because they have laid their DIP ICs on a 0.1" grid and nobody leaves only 0.1" between adjacent ICs, it’s at least 0.2", or more if there is a decoupling capacitor, so there is a bit of room.
Edit: Are you sure there are 14 pin chips 20 mm long? Subtracting the gaps between 7 pins, 15.24 mm leaves 4.76 mm so 2.38 mm overhang each end. That’s almost 0.1". I know however that there are 16 pin chips that are shorter, the pins at the corners look like half pins.
If you really have chips that long, then generate your own footprints with the wizard, you can specify the courtyard. It’s part of the design process, making sure the parts fit into the allocated space.
I thought that happened only to me. Many years ago the 4 AA cells leaked onto the socket for the CMOS memory chip (or something like that) and that killed my 80386 computer.
Yeah, the NiCd cells powering the CMOS clock and config memory used to do that too. Lithium button cells eventually solved that.
DIP-14 usually have fully formed pins, and it’s case has the same length as a DIP-16, but this is not so in the (Script generated?) 3D model in KiCad. KiCad’s 3D models of DIP IC’s all have their pins cut of fin the corners.
Electronics getting damaged by leaking batteries is unfortunately quite common.
When alkaline batteries start leaking, the electrolyte is a liquid and this dries out and crystalizes over time and then leaves a conductive and aggressive residue.
Dave caught a wet battery in EEVblog #1349 https://www.youtube.com/watch?v=YZCPlbOuxJY
Damage from leaking batteries is easy to avoid by adding a piece of absorbent material around the battery, but manufacturers are not interested in such a 10ct solution because batteries usually start leaking after the warranty period has expired (And it’ often is even explicitly excluded from the warranty) Result is they save a few cents, and they sell more gadgets. Double win for them.
I have seen those, the body is the same size as a 14-pin DIP.
I have seen those stunted 16 pin, but the courtyard should follow the larger option. I have seen DIP boards (long ago) where the ICs are too close and the decoupling is a struggle to fit.
The problem is… Update it to what?
A quick searched showed quite a few DIP with varying maximum outlines.
Maybe an unpopular opinion, but the most common dimension, not the largest. I don’t see any reason to make everyone spread their DIPs out way too far because someone makes a random DIP the size of a football field. If you use an unusual part, it’s your responsibility to make it a footprint. And if you use any parts at all, it’s yours to check that the default footprint is suitable
Can you give examples of the outliers?
Chip makers often buy in their lead frames so anything very unusual would have to have a reason
I’m with @alexisvl on this, the designer should be checking and if the kicad stock footprints don’t align with the parts being ordered than a local part specific footprint is needed - every now and again you end up with a part where a JEDEC outline is mentioned and it isn’t
This one almost caught me out: https://www.bourns.com/data/global/pdfs/PWR163.pdf
An early revision stated “DPAK” (it now states: The PWR163 Series is a DPAK style … Smaller than a D2PAK package) while the mechanical was always correct
Looking at your examples, you need to allow a length of 20 mm to cope with a maximum device and not quite centred in the holes
TI, who are about the biggest brand left these days have 14 and 16 pin both the same at 0.775", 19.69 mm maximum, so I would say that the courtyard was intended to be 0.8" in a 0.1" pitch world
Strangely the 3D models for 14 pin and 16 pin are the same length, so matching TI etc reality
I have not done much research on this, but to me it looks like DIP-14 is a real outlier here.
As far as I know most narrow DIP packages have the “half pins” in their corners except DIP-14 in which all pins look the same… (And has indeed the same length as DIP-16) The Wide dip packages (old eproms, Z80 and other IC’s from that era) also have fully formed pins.
I’ve also got a bunch of old Cache schips from old 80486 computers (32kB RAM) from various manufacturers, and these come both with full and with half pins in their corners. All are (approx) 14*2.54 = 35.5635mm long though. (That seems to be the upper limit of the package.
A squiz through my junk box of hundreds of ICs shows that the half pins are actually in the minority, and tend to be associated with the 16 pin and 20 pin packages when they are used. I think if you’re still working with DIP packages it’s advisable to leave some tolerance, most likely between the package and the decoupling capacitor, or to measure the actual chips you will use in production, but then what will you do if you’ve made the clearances too tight and your supply source changes?
The chip makers often use sub con package and test, so even in one brand you might find variation. Making the 14 pin courtyard the same as the 16 pin would be the safest option.
This topic was automatically closed 90 days after the last reply. New replies are no longer allowed.
