Differential pair through bus


#1

Dear all,

I’m using a hierarchical schematics and to different part of the circuit, I’m using buses. Through these buses I need to connect some USB3 lines which contain some differential pair. So I’ve made this:

USB3 hub.pdf (347.7 KB)
cam.pdf (231.3 KB)
main.pdf (130.5 KB)

My problem is I’m not able to route these line like differential pairs in PCBnew.

Does any one have an idea ?

Best

Jerome.


#2

The net names of the pairs need to end in a specific way to be counted as a differential pair.
I think the correct endings are + and - (I remember there were other options but i can’t find any documentation about it.)


#3

#4

Which is a bit silly. Names should not have any meaning to KiCad. Prevents the use of industry standard names like CANH / CANL.


#5

How do other pcb design software packages handle this sort of thing?
(How does the user tell the software which signals are a differential pairs?)


#6

The name should be fine cause it works for other lines. But It seems the name saved by kicad in PCBnew is the name of the bus. Like : A1_USB3_5

I used Eagle before and they use the same principle for pairs lines should end by P/N.


#7

As far as I know both Eagle and Altium also require the suffixes _P/_N.


#8

Altium requires you to put a differential pair routing directive on all nets to be routed as such, and the signals in each pair must have the _P and _N suffixes.


#9

So nobody have an idea on how solving my issue ?


#10

The first answer was right: label your differential signals with the same name, one ending with “+” and the other one ending with “-”


#11

I did it with _P / _N who should work as well but it didn’t. (check the print screen) I can try with +/-


#12

I fear that your local label USB_D1_SSTX_P is overwritten by the second local label A1_USB3_4.
I’m not sure there is a solution that allows both the usage of buses and differential pairs.


#13

It works for another type of net I’ve made the same way. I’ll show you a bit later.
I don’t know if there is a way for giving priority to net name.


#14

Nope there is not. If you have two labels (with the same weight. example two local labels) one of them is chosen “randomly”. (Unspecified behavior.)
They might be chosen by: last one found, first one found, the left most, the rightmost, …
In the worst case the unspecified behavior could mean that someone with a different kicad version gets a different result!

The official docu is not a lot of help here:
http://docs.kicad-pcb.org/stable/en/eeschema.html#wires-buses-labels-power-ports


#15

Thank you very much. I’ll try to find a way, maybe by removing the bus. Do you know where I could report feature request for future development ?

Thanks for the help.


#16

I think i read somewhere that the buses might get implemented in a more intelligent way.
(I can’t find it at the moment. So maybe i’m wrong about that.)

But to answer your question:

  • Wishes for features need to be posted on the bugtracker with ‘wishlist’ as tag
  • Pure wishes, without support by a Dev or a patch ready to go into the KiCAD code have a very small chance of ever being implemented.
  • Document your wish as good as possible. The better it is documented the better the changes a develober will look at it.

The side to report bugs/wishes can be found under:
https://bugs.launchpad.net/kicad
(In case you want to post there, search for 15 minutes if anyone else has already posted a similar wish. If so: mark it with “this bug affects me too” instead of creating a duplicate bug.)

Here also the link to the official “how to” page for reporting “bugs”: http://kicad-pcb.org/help/report-a-bug/


#17

Ok, great, thank you for the information.

I’ve finally found a way to solve my issue while keeping the buses. I’ve just added a global label to each net with the _P/_N at the end. The global label takes priority on local one so problem solve.

Thank you all.

Jérôme


#18

This solution only works if you instantiate your hierarchical sheet only once.
Maybe make a note near the labels such that you remember that. (Otherwise you might make a mistake a few years down the line.)


#19

Here are the dialogs for setting up DPs in Allegro:

dp1dp2


#20

You can see Allegro allows arbitrary suffix selection for the positive/negative nets in the DP, and the DP gets a unique name in the Constraint Manager tool to allow both nets to be constrained relative to other elements.

And in PADS (which I’m not familiar with):