Differential Pair routing


Hi , I am new to design differential pair routing for ethernet. I am designing 100Mbps speed of ethernet connection.
I have a doubt

  1. My controller is TQFP package means how to calculate track width, trace width and trace gap for differential pair?
  2. If i want to match the characteristics impedance means whether it depends on trace width/track width/trace gap?


The package barely plays into it,

To properly answer your question, the key things are:
2 layer or 4 layer?
Board Thickness?
Copper Plating Thickness? E.g. normal 1oz, or something different.
If its 4 layer, what is the plane to outer layer spacing?

And the key one to know if you even have to worry about it. How long is the distance between the controller and what it connects to, as if your beneath 75mm in length for a maximum frequency of 100MHz, its not really in the frequency range where impedance matters, And it will probably end up at 0.25mm trace, 0.2mm gap,


Thanks for your reply,
In my controller data sheet, they had mentioned that for 4 layer board Width is 12 mil (0.3048 mm) and gap is 24mil (0.6096mm) and also they mentioned not less than 2 inch(50.8mm) track length. but when i routing the differential pair, controller pad cannot able to accept the size, i am using arm based controller. For your kind information controller has 120Mhz normal frequency


So your board is 4 layers or 2?
What is the thickness of the PCB?
If 4 layers what is the gap between the inner and signal layer?

Still lets use what you have to estimate what assumtions they are working on.
So for 0.3mm trace, 0.6mm gap, and assuming a 0.18mm gap between signal layer and inner layer, you end up with 89.7 Ohms Differential, and 45.7 Ohms single ended. so looks a lot like USB requirements.

However my calculator says this is a poorly coupled differential pair due to the large spacing vs gap to ground plane.

for the same system, a 0.25/0.25mm setup has much better coupling for the same impedances more or less,

For clarity this stuff is calculated using the “Saturn PCB Toolkit” program.


I should also add that for routing into your IC, its not critical to maintain the spacing and width right to the last mm, generally a few mm out from the chip pads you switch to a suitable track width, if the calculated ones are too wide.

The 50.8mm length constraint is an odd one, more than likely that the margin you must match lengths of the various communication pairs to, as that is only 300ps of delay.


Hi sir,

If I want to match the characteristics impedance of 100ohm for each
differential pair, wat will be the track width and gap and how could i

Quoting Ryan info@kicad.info:


I am designing ethernet differential pair not USB routing


For differential pair routing to ethernet, which transmission line type can be used microstrip or stripline is preferred


Hi sir,
In that image they had mentioned that for 100ohm +/- 10% impedance is ethernet and 90ohm +/- 10% impedance is USB. Kindly help me to complete the differential pair routing


So your board is 4 layers or 2?
What is the thickness of the PCB?
If 4 layers what is the gap between the inner and signal layer?

These calculations I am running for you are more or less pointless unless you can answer ANY of the above!
This stuff is dependant on those dimensions, if they are different, they will not match up.


For microstrip vs stripline, it would actually be an Asymetric stripline, as most 4 layer boards will have a larger gap between the inner layers than the inner-outer, In reality unless your really running out of room, or near a horrible noise source, I would always trend towards microstrip,

  1. I am using 4 layers board
  2. Thickness of the PCB board is 1.6mm
  3. For inner layer to signal layer gap will be 0.2032mm. If you have doubt kindly verify my attachment in previous


That is the recommended stack-up from the datasheet, not the one provided by your manufacturer?

Just in case you where not aware, unless they specify it, you may end up with just about any stack-up to suit the one customer who paid for a certain stack-up that you end up sharing a panel with.

Anyway here you go.


Hi Sir
Thank you so much. I have another doubt while routing the differential pair to RJ45 connector i could not able to route with 0.3mm width, it can able to route with single track width like 0.15mm. whether shall i do it or not and also my microcontroller routing also having the same problem
Pls guide me.


Route it at the proper width as close as you can, then jump to thinner close to the pads,


Thank u sir
Becoz of this any issues will happen??


Not at all, again you can have up to 75mm of non impedance matched traces before you get issues, so 1mm at the pads is nothing.


Please note the following:

With the latest example calculation (image 3 replies above), it is necessary to have H = 0.203mm.
H is the thickness of prepreg(s) between your top layer and layer 2.
You must ensure that your PCB supplier produces according to this requirement.
This normally results in a custom layer buildup = extra costs.

Economically, it would be best to find a supplier with a given H and adjust your other parameters (w, s) accordingly.

Example: Multi-CB offers a defined stackup for 4 layers with H = 140µm (0.140mm).
This results in the following parameters for s and w, which are free of charge for the supplier:

Calculations can be done here: https://www.multi-circuit-boards.eu/en/pcb-design-aid/impedance-calculation.html