Which is a case by case decision and Er variation is just only one parameter, tolerance in etched trace width can lead to much greater spread, especially for a high impedance line.
Reading a bit about USB3, you get 85R traces, 90R cable and the I find this article aiming for 100R
I won’t deny that it gets confusing. The USB3.1 standard makes no mention of 85 Ω impedance, all three differential pairs have a differential impedance of 90 Ω. I believe the tolerance for USB3 is +/-5 ohms.
The standard also states The eye diagrams are to be measured into 50-Ω single-ended loads. which is why the document you posted was using 100Ω differential pair.
I found a TI pdf stating 15% for USB3.0
The loss and crosstalk seem to be more critical than the impedance
That’s not true at all. Controlling impedance is one way to control losses since impedance mismatches result in losses. The crosstalk usually discussed in reference to differential pairs is the crosstalk caused by adjacent pairs/channels. The crosstalk within a differential pair manifests as loss, the tighter the coupling the greater the loss. This is one reason why with high speed signals you would use looser coupling. Dielectric loss for a given impedance and frequency remain fixed for a given substrate material. Conductor loss is a function of trace width and length. Looser coupling allows for wider traces reducing conductor losses. An increase in substrate thickness also allows for wider traces again lowering conductor losses. And of course, shorter traces also reduce conductor loss. All while maintaining the desired characteristic impedance.
There is no perfect solution only trade-offs. Wider traces and spacing consume board real-estate. Looser coupling increases sensitivity to crosstalk from adjacent signals as does an increase in substrate thickness as it increases the distance to your reference plane.
Hi Seth,
I’ve made some experiments with IPC-D-317 and IPC2141A formulas that I compared to results from Polar Instruments SI9000, Hyperlynx, ICD stackup planner and Alter-PCB. After modeling IPC formulas with Excel, it was pretty easy to check results. All software using solvers give about the same results (around 1% error for any value of H, W, T, Er and S). IPC approximations are far from these commercial softwares. IPC formulas are a real nightmare to compute differential and asymmetric stripline impedance. Do you know what formulas are used in Kicad calculator?
For me three extra calculations are missing: signal velocity and trace inductance and capacity to prepare transmission line simulation with Spice.
Thanks again for the great job you’re doing at Kicad.
Mecagigi.