Different GND and VDD but still connected

Hello
my problem is that i created different GND and different VDD like AGDN, AVDD, DGND.
But when I test with the “Highlight Net” they are all connected as you can see in the image below.




I use kicad 7.0.7, release build
Thank you for any help you can give me,

Basil

Have you used net ties to connect them together?

If you used a simple wire in the schematics editor, it’s normal that KiCad would consider them one net.

How did you create those additonal GNDs? By taking GND and editing the label? That’s a common trap. You have also to change the label on the pin inside.

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There is no AGND symbol in KiCad’s default libraries.

What is the origin of these symbols? Did you make them yourself?
KiCad’s power symbols are still a bit of a kludge. They act as global labels, but name of the net is not derived from the symbol name, but from the name of the pin in the symbol, and that name is also hidden in the schematic. In the screenshot above it is the cyan text, and not the green text at the bottom of the symbol.

If this is the cause of your trouble, then you have to modify these symbols yourself in the symbol editor, and replace the symbols in the schematic with the updated versions.

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thank you for the reply
i take note

Hello, thank you for your reply
as you said, I didn’t name the pin and I didn’t assign it a number, like the ones in cyan text on your image.
that’s why all the different GND and VDD I’ve created are connected together
It was a bit stupid of me

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Not really.
It is is not very logical to do things this way in KiCad. It has been fixed in the nightlies, and in KiCad V8 (Expected February 2024) power symbols are implemented in a different way and you can just change a text string in the schematic to use it for a different net.

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hello
in the continuation of the thread above i would like to connect a label who is connected to a output from an analog device to a power input(AVDD) that i created
why that didn’t work ?
clk_vdd

i use kicad 7.0.7
thank you if someone can help me
Basil

Why do you think it does not work?
Are those screenshots from the same page?
What is the ERC message belonging to that arrow?
What is the name of the net connected to pin 26 of that IC?

I’m not sure if it is for always and ever, but for me label have their reference point at bottom left of text and it worked for me ‘since always’. I don’t remember rotating labels ever so may be when rotated something changes, or may be there are some settings I have never used.
For me your CLK_VDD has nothing at its reference point.

Nope. There is no problem with rotated labels. When the little square disappears, the label is connected, either to a wire, bus or directly to a pin.

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So as we don’t see little square (left down of text) here that means that it was probably at right down of text and disappeared because label is connected to this wire end?

Yes. Labels can be rotated and mirrored to get the attachment point on another corner.

But the attachment point is apparently always at the baseline of the text, and this is good, because it reduces confusion then there are a lot of labels packed together in a row or column.

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-Yes they are in the same schematic.
-The ERC message is “AVDD and CLK_VDD are attached to the same elements.” I don’t know if it’s the same error name in English because I just translated it from French .
-The pin name is “PLL/DLL_VDD”
Thanks for all the reply

Your translation is close enough. Here I recreated the English version:

And it is not an error. Actually KiCad is informing you that the two nets are connected. Both power symbols and labels generate a net name, but a net can have only one name, and therefore, KiCad has to choose one of the names.

KiCad puts it in ERC because it can be an error / mistake. For example from a misspelled label name. If you have confirmed it is OK, then you can right click on the warning message and click Ignore this violation. This puts it in the Exclusions list and KiCad will not show the message again on the next ERC run.

okay thanks for the answer :+1:t2:

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