Working around this one with a script to dump track lengths on the DDR interface and other things that could benefit from length matching and add the pad to die length. Note the hard coded U1 that is the CPU. That is a bit of a hack.
#!/usr/bin/env python
import sys
from pcbnew import *
pcb = LoadBoard(sys.argv[1])
tracks = pcb.GetTracks()
td = {}
mod = pcb.FindModuleByReference('U1')
pads = mod.Pads()
for pad in pads:
name = pad.GetNetname()
length = ToMM(pad.GetPadToDieLength())
td[name] = length
for track in tracks:
name = track.GetNetname()
length = ToMM(track.GetLength())
if name in td:
td[name] += length
else:
td[name] = length
addr = ['/dram/DDR_CK-',
'/dram/DDR_CK+',
'/dram/DDR_BA1',
'/dram/DDR_BA0',
'/dram/DDR_BA2',
'/dram/DDR_A5',
'/dram/DDR_CKE',
'/dram/DDR_A12',
'/dram/DDR_A13',
'/dram/DDR_A10',
'/dram/DDR_A14',
'/dram/DDR_ODT',
'/dram/DDR_A11',
'/dram/DDR_RAS_B',
'/dram/DDR_CAS_B',
'/dram/DDR_A8',
'/dram/DDR_A9',
'/dram/DDR_A0',
'/dram/DDR_A1',
'/dram/DDR_A2',
'/dram/DDR_A3',
'/dram/DDR_A4',
'/dram/DDR_A6',
'/dram/DDR_A7',
'/dram/DDR_WE_B',
'/dram/DDR_CS_B']
dq0 = ['/dram/DDR_DQS0-',
'/dram/DDR_DQS0+',
'/dram/DDR_DQ6',
'/dram/DDR_DQ3',
'/dram/DDR_DQ2',
'/dram/DDR_DQ1',
'/dram/DDR_DQ0',
'/dram/DDR_DQ7',
'/dram/DDR_DQ5',
'/dram/DDR_DQ4',
'/dram/DDR_DM0']
dq1 = ['/dram/DDR_DQS1+',
'/dram/DDR_DQS1-',
'/dram/DDR_DQ9',
'/dram/DDR_DQ8',
'/dram/DDR_DQ13',
'/dram/DDR_DQ12',
'/dram/DDR_DQ11',
'/dram/DDR_DQ10',
'/dram/DDR_DQ15',
'/dram/DDR_DQ14',
'/dram/DDR_DM1']
def plist(nlist):
count = 0
length = 0
for net in td:
if not net in nlist:
continue
print net, td[net]
count += 1
length += td[net]
print length/count
print "\ncontrol"
plist(addr)
print "\ndq0"
plist(dq0)
print "\ndq1"
plist(dq1)
print "\nDAC"
count = 0
length = 0
for net in td:
if not "DACD" in net:
continue
print net, td[net]
count += 1
length += td[net]
print "\nRGMII"
count = 0
length = 0
for net in td:
if not "/mio/ENET" in net:
continue
print net, td[net]
count += 1
length += td[net]