DFN Placement Disaster

My first time using a DFN; I notice that all of the DFN footprints in the KiCad libraries have a long silkscreen line at the bottom of the part (farthest from pin 1), whereas pretty much every other IC package family (SO, QFP, TSOT, etc) uses a long silkscreen line to denote the pin 1 side.

When I saw the first one, I said “Oh, this is an error in this library part”, but then I saw that all of the DFNs are like this. So I said “OK, I guess this is the standard for DFN”, and “the assembler will get the correct orientation from the fab layer and the POS file”.

Well, guess what, the boards came in today and they assembled them with pin 1 toward the big line :frowning:

What should I have done differently? And why doesn’t the DFN silkscreen in KiCad libraries follow the same convention as every other package family???

You are right, there’s no real convention for this in KiCad’s libraries. First I thought that “something which deviates from the package outline”, but then…

So there just isn’t any logic in this. And it’s wrong.

That said, it should really be the assembler’s responsibility to check the fab layer and the pos file. They just can’t assume that all footprints in a board obey the same rules. Looking only at the silk layer can even be seen as obsolete. Not all boards even have the silk layer, or are too dense to have reliable graphics everywhere.

You could have given a note that “assembly (Fab) layer is the authoritative guide for assembly” or something like that and then check all fab outlines and markings before you generate the gerbers. The information can also be added to other layers: the copper pad 1 can be different shape (rounded or non-rounded or with fillet) and even the mask can be different (if the manufacturer allows). But nothing helps if the assember looks only at the silk layer blindly and assumes things.


I agree with @eelik . Unfortunately i do not have an answer on your last question, but if you sent them the fab layer this is 100% on the assembler. (EDIT: If they were not sure, they should have asked.) Silkscreen is an optional assembly layer as far as i have see. Did you asked them why they chose to ignore fab layer?

Agreed. Or at least 98% :slight_smile:

Agree totally. And during the run, they asked about a number of other things - they’re not shy.

Agreed, it’s cosmetic

I pointed out that the orientation was supplied in the fab layer and POS file. Have not heard back from them yet. Fortunately they still have most of the batch there and I’ve asked them to re-work them.

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I have been trying to find any kind of standard for pin 1 marking, but can’t find any reliable information. This is surprising because rotating components for assembly is critical and happens for every board, and is a common source of mistakes. Just like many other things in manufacturing (and assembly) it relies on ad hoc communication more than any formal file features.

If there is no actual standard then should these marks simply be removed?

From what you see of the imprint that QFN the long line of screen printing is located from the part close to pin 1 not far from pin1.

For me the footprint is correct.

They are still helpful for manual assembly, rework, debugging etc.

Yes, maybe that wasn’t a very good illustration, but shows that my initial hypothesis that something which doesn’t follow the component outline is pin 1 mark was wrong, and it shows that KiCad libraries don’t follow any logical rule in general. Look at the silk line at the bottom of the footprint. I don’t know why it’s shorter. This footprint really has two pin 1 marks which isn’t necessarily a bad thing, but the 90 deg corner may go on another component’s pad in a cramped design.

But I saw that some DFNs follow a logic as you mentioned.
It should be reset like the others in my opinion.

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I can report inconsistency in the gitlab section “KiCad Footprints” .
What do you say?

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That’s a WSON, not a DFN. I think eelik posted it to make another point.

Here’s what the KiCad DFNs look like:

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I say “Yes, please, and thank you!”

I hope I have explained the problem well.


An erudite big report! :+1:

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I manually add a pin 1 silkscreen dot for these. It just seems wrong to indicate pin 1 with lack of silkscreen.


in kicad i.e. DFN-8-1EP_4x4mm_P0.8mm_EP2.39x2.21mm.kicad_mod
version 5.1

version 6 and 6.99

IMO kicad v5 was correct and v6 and v6.99 is wrong

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Personally I haven’t had any issues with this (neither hand assembling or external assembly).

Find 3 sides which are all mirrors of each other, the one which is not is pin 1.

Adding a longer pin 1 is hard on no-lead packages, and would make the silkscreen much bigger than the package itself. Not nice for high density layouts.
The difference between the short and long silk line gets harder to see on a 2x2mm package. Normal silk line vs no silk corner is much easier to see IMO

Exporting fab layer is highly recommended

Related library discussion a while back

The problem does not arise for chips with pins on 4 sides but for those that have two sides where the logic of screen printing is contrary to the logic used in all the other 2-sided chips such as PDIP or SOIC
I realize that for DFN the dimensions are very small.
My opinion is that the new design logic of screen printing confuses ideas.

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