Hi there,
I have a question about routing and DRC.
Is there a possibility for DRC to detect Tracks that don’t fulfill a purpose?
To show what I mean, I made a little example.
The Track with two vias under R1 is obviously completely useless.
I know this is a very unusual scenario but is there a way to “remove excess tracks and vias”?
You didn’t really need to draw the loop to satisfy DRC. The track shorting the two pads of R1 satisfies the schematic.
I had a look at the DRC constraints and couldn’t see one that would do what you asked for . . .
Interactive routings settings should help if you have “Remove redundant tracks” enabled . . .
That’s the issue.
I would like to find a way for DRC to detect if I did too much.
So the DRC should detect exactly what you said. The shortest, most efficient track that satisfies DRC should flag my loop as obsolete.
i suspect this is a problem much more complex than the ones usually detected by a DRC algorithm.
Unfortunately the remove redundant tracks feature only works between two connected points.
My question actually originates from a colleague of mine who is only used to Eagle but forced to adopt KiCad now. He asked me this exact question in the context of editing schematics after routing.
Like he had a connection routed, then swapped a pin in schematic.
DRC obviously threw a couple errors, since the pads were contacted incorrectly.
Now he just deleted the small stub that connected the actual pin and left the majority of the original track as it was. Then he drew a new track and connected the pad correctly.
As a result there was a correctly connected track, thus no errors in DRC.
Yet the “open” track still remained and wasn’t flagged as an error or warning.
I personally would never try to just partially delete a track and then proceed to re-route it from it’s origin, so this scenario was very unlikely in my eyes. But since I now witnessed this exact case, I was wondering if there is some kind of constraint that could prevent such “blind” tracks.
edit: I just found out my scenario only didn’t throw an error, since it was a “loop”.
Open tracks actually do get detected. Yet my colleague kinda routed the connection in a “ring-architecture” so the DRC didn’t detect it.
Seems like it. I was just curious if maybe KiCad already had something like that and I just didn’t find it.
What I pointed out is that your schematic is not the minimum. All you need to create a loop is one pin one net, then you can draw a track loop on it. How would KiCad know whether it’s useless or not? It violates no rules. Maybe you want a looped track? Maybe it’s for decoration?
It’s not so simple. KiCad can not assume you want the shortest track, or otherwise attempt to guess your intentions. Sometimes redundant tracks are added to improve current handling capability. The shortest track is not always the path of lowest impedance, and then there are also things such as length matching and PCB antenna’s. KiCad is just a fancy drawing program with extra rules to make PCB design easier (Just like all the other PCB design suites) and it’s up to the user to put in some intelligence and make good decisions.
