One thing that seems to be missing is class to class DRC rules. High voltage designs require DRC rules within the class and class to class. Does the ability exist or is it being considered?
I don’t understand what you mean by “class to class” or even “within the class”, can you explain?
I have previously done high voltage designs in Altium. With something like a gate driver there are clearance rules between the traces within a group of nets associated directly with driving the gate. There are also rules in the control side. Between the two there would be a high spacing requirement. By defining the nets on the gate drive side as a class and those on the control side as a class there is then a need to have a class to class rule defining the clearance between the sets of nets (the classes).
As an example, IEC defines a circuit region as SELV. There are also usually medium voltage nets (a class). In addition there are nets associated with chassis ground. They all have their own internal clearance requirements and requirements between the classes depending upon the insulation / exposure level.
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It is the same. There are IEC rules that define this.
As v5 is in feature freeze, this one is going to have to wait for the next round and a willing developer
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