Hi everyone,
I’m designing a small board for the TPS65130/65131 which is a buck and inverter DC/DC converter. So single supply (2.7-5.5V) to dual supply (maximum -15V/+15V). So pretty useful for USB (5V) or from a single 3.3V supply.
So I’d be glad if you guys can do a design review about the layout. I’ve attached the schematics and the annoted layout. I’ve not specified the values of the components yet. In fact, they’re dependent about the outputs you want, and the way you want to optimize for your application.
It’s actually a “reboot” of a previous project (GitHub - anotherlin/olympic-white: A DC/DC converter module based on TPS65131 to provide adjustable positive and negative rails from a 2.7V-5.5V supply.) that I started and then left because the first try was unsuccessful. Everything will be on github when it’s done. I can send the Kicad project if needed for the review.
The schematics is basically the “typical application” of section 8 of the datasheet. I’ve added extra output capacitors, it may be cheaper to put 2 instead of 1 big capacitor. And I’ve added the extra resistor to lower noise for the feedforward capacitor in the feedback dividers.
Here are a few comments:
- 2 layer board, everything routed on top, except jumper bridges JP1 and JP2 to select power-save mode;
- Power ground (GND) and analog ground (earth) are connected at U1 on the bottom pad (25);
- L1 (boost) and L2 (inverting) inductors as close as possible with U1. I’ve annoted the switching loops which are as tight as possible;
- Feedbacks as close as possible but separated from the switching loops to try minimize noise;
- VPOS and VNEG signal routed rather close to the switching components, but probably used for over-voltage protection, should be ok regarding noise;
- enable/disable (ENP and ENN) and power-save mode selection (PSN and PSP) routed on bottom layer. I’ve tried to route them “away” from the feedback components so they have a nice ground bottom layer to “shield”.
Here are a few questions I’m wondering specifically:
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Did I do any gross mistake regarding the layout? Please help me on this one!
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Power ground and analog ground handling:
Power ground (GND) and analog/signal ground (Earth) are separated but connected together on pad 25 of U1. I’m using cable tie NT1 in schematics. In particular, VIN that supplies the TPS6513x (U1) controller is “made” (filtered) from V_in (input supply) using R7 and C3. “Typical application” schematic connects C3 to analog ground. This is also the case for PSP and PSN controls and enables. Is that really necessary to connect C3 to analog ground? In my case, that routes a wire on bottom layer using 2 vias.
I understand the necessity for noise reduction purpose to separate grounds. And I have taken special care to have the feedbacks resistor dividers separated from the switching as much as possible. Note that he analog ground (“Earth”) is routed on top layer for R2, C6, C7, and C8. But for C3, is that really necessary? This is the power for the controller and internally it will do some switching. -
Dedicated GND trace on top layer vs. copper fill/polygon?
Top layer uses copper polygon/pour to route GND. This can be done using a pour instead (like for bottom layer), should I do that instead? -
Is vias under inductor (L2)?
I’m routing ENP/ENN (outputs enable/disable), and PSP/PSN (power-save mode), using vias under the inductor L2. They are basically constant DC voltages Is that ok?
I need to finish a few things, like the silkscreens and may be add some more thermal/stiching vias.
Thanks for your feedbacks and suggestions.
Best regards,