I’m designing a small board for the TPS65130/65131 which is a buck and inverter DC/DC converter. So single supply (2.7-5.5V) to dual supply (maximum -15V/+15V). So pretty useful for USB (5V) or from a single 3.3V supply.
So I’d be glad if you guys can do a design review about the layout. I’ve attached the schematics and the annoted layout. I’ve not specified the values of the components yet. In fact, they’re dependent about the outputs you want, and the way you want to optimize for your application.
The schematics is basically the “typical application” of section 8 of the datasheet. I’ve added extra output capacitors, it may be cheaper to put 2 instead of 1 big capacitor. And I’ve added the extra resistor to lower noise for the feedforward capacitor in the feedback dividers.
Here are a few comments:
2 layer board, everything routed on top, except jumper bridges JP1 and JP2 to select power-save mode;
Power ground (GND) and analog ground (earth) are connected at U1 on the bottom pad (25);
L1 (boost) and L2 (inverting) inductors as close as possible with U1. I’ve annoted the switching loops which are as tight as possible;
Feedbacks as close as possible but separated from the switching loops to try minimize noise;
VPOS and VNEG signal routed rather close to the switching components, but probably used for over-voltage protection, should be ok regarding noise;
enable/disable (ENP and ENN) and power-save mode selection (PSN and PSP) routed on bottom layer. I’ve tried to route them “away” from the feedback components so they have a nice ground bottom layer to “shield”.
Here are a few questions I’m wondering specifically:
Did I do any gross mistake regarding the layout? Please help me on this one!
Power ground and analog ground handling:
Power ground (GND) and analog/signal ground (Earth) are separated but connected together on pad 25 of U1. I’m using cable tie NT1 in schematics. In particular, VIN that supplies the TPS6513x (U1) controller is “made” (filtered) from V_in (input supply) using R7 and C3. “Typical application” schematic connects C3 to analog ground. This is also the case for PSP and PSN controls and enables. Is that really necessary to connect C3 to analog ground? In my case, that routes a wire on bottom layer using 2 vias.
I understand the necessity for noise reduction purpose to separate grounds. And I have taken special care to have the feedbacks resistor dividers separated from the switching as much as possible. Note that he analog ground (“Earth”) is routed on top layer for R2, C6, C7, and C8. But for C3, is that really necessary? This is the power for the controller and internally it will do some switching.
Dedicated GND trace on top layer vs. copper fill/polygon?
Top layer uses copper polygon/pour to route GND. This can be done using a pour instead (like for bottom layer), should I do that instead?
Is vias under inductor (L2)?
I’m routing ENP/ENN (outputs enable/disable), and PSP/PSN (power-save mode), using vias under the inductor L2. They are basically constant DC voltages Is that ok?
I need to finish a few things, like the silkscreens and may be add some more thermal/stiching vias.
You didn’t finished one of V_pos switching loops. Pulse current goes from C4 GND to C1 GND and I think this connection could be shorter. C4,C11 need not to be close to J3 - there you have no switching current.
From EMC point of view the best is if two loops are close to each other. I imagine loops are light alternately and I am trying to make distance from PCB you will no notice flashing as short as possible.
If there were only C4 (without C11) I would consider placing it over a track from IC to L1 pin 2. So C4 and C1 GNDs would be together.
But not assume me being an expert in DCDC design - I have designed only few PCBs with it and never with dual output.
A few comments outside of the functionality of the switching chip:
I see you desire ± 15V outputs, but did not mention what the maximum output current should be… Always nice to have the full specs for the design
You just have electrolytic or tantalum caps on the inputs and outputs of the chip. The ESR of the caps will be important. I would parallel some ceramic monos to the caps for lower ESR and better ability to provide peak currents. A 10 uF 50V 1206 part is easy to add, and then put in a .1 uF also in parallel to keep things EMI quiet.
Any time you have a switcher, it’s nice to provide some EMI filtering on the inputs and outputs before you get too far away from the switcher. Vishay has some nice 1206 ferrite beads rated at 500 ohms @ 100 MHz, 2.5A, 60 milliOhm. Put them on the inputs and outputs, with a 1 nF on the outside facing connections. The Texas Instruments site has some good filter examples in it. Finally design depends on just how the supply fits into the entire system. The only thing more expensive than a few extra parts is re-working the entire design to add them later.
TI reference designs are typically the bare minimum. If the data sheet has any “recommended layout” example, be sure to follow them.
If you’re using OshPark, remember they have a .032" 2 oz copper board. I’ve used them a lot on small power supplies.
All that said, it is indeed a challenge in some applications to make everything work on a 3.3 to 5V supply. The need for more room between the rails seems to happen a lot.
Best of luck on your project. If you have the luxury of throwing the 1st one out so you can benefit from what you’ve learned, take it.
I had in my mind that ferrite beads not resonate so didn’t worry about it at all.
I powered RS485 driver via 1k ferrite bead + 100nF. Recently I found that when RS485 driver switches output state (takes pulses around 200mA) to opposite its VCC drops from 3V3 to 2V3 (don’t remember exactly). The reason - ferrite bead inductance (around 3uH). I²L=U²C. U = sqrt(L/C)*I = sqrt(3/0.1)*0.2 = 5.5 * 0.2 = 1.1V.
500 ohm ferrite bead will have smaller L but working with 1nF…
I was thinking that since the beads would be at the input, presumably a DC source, and had an output, presumable a DC output, that this would be OK. If indeed the output was powering things that can quickly change their current draw, then a more detailed design is needed.
Some of the TI notes/datasheets on filter for switching supplies go into better detail of all this, and show some good examples of how to avoid unwanted resonances (typically involving a resistor in series with the filter cap). Good reading there.
I use a lot of the Vishay ILHB series, and they have a nice spread of impedance, part size, and DC current rating. The spec sheet also shows you how “sharp” the impedance is with frequency. Like a lot of people, I fall back to various “go-to” parts or family of parts.
Nice math there, and you make a very valid point. Of particular interest is that most of the ferrite bead data sheets don’t mention the inductance. So for any given EMI reduction design, you need to test, measure and verify what is really going on.
Thanks for the good example !
So yes, as @Piotr mentioned, the second loop of the boost converter is wrong. It has too be tighter and I’ve corrected that. I thought that because the inductor was in series, this wasn’t a problem. But in fact, it seems the output capacitors are the most important components in a boost converter
(Five Steps to a Good PCB Layout of the Boost Converter).
Most importantly, it seems that the placements of the free wheeling diodes is especially important and must be placed as close as possible to switching pins of the IC. I thought it wasn’t important as the diodes conduct only when the switch is off to discharge the inductor to the output capacitors. And was rather trying to optimize the distance between the diode and output caps. But seems that’s important regarding spike noise, and hence all “recommende” layouts I’ve came across have the diode closer to the switching node of the IC. In fact, closer than the inductor is (PCB Layout Techniques of Buck Converter)
It’s not necessarly +/- 15V, the goal is rather to have a board with a few fixed components (TPS65131, schkotty diodes, and maybe the EMI input filtering). The end-user soldering the feedback resistors, appropriate inductors and capacitors to
“dial output voltages”. In fact, it may be +/- 14V to be followed by LDO so as to have really clean +/- 12V. The board/module is breadboard friendly (2.54mm pitched) .
All capacitors are ceramics, I should modify the schematics and replace the polarized ones. I also have to add extra parallel 0805 caps for 100nF for both input and output capacitors.
I just didn’t wanted to blindly copy a “recommended layout” without trying to understand it. I don’t understand it better now, but I will follow their recommendation for the time being. I still have my electromagnetism textbook and I will now seriously dig it now, which I should have done at university
I use JLCPCB and it’s so cheap (quote is 4 euros for 5 pieces) that I can even afford to make that first iteration to see how bad it is and learn something.
Plenty of work for the 2nd iteration of the board.
The 3 references you have from TI are just what you need. They identify all the key layout concerns and have a good tool for input filtering.
In KiCad, I made some custom footprints. They are:
12060805, 08050603 and 06030402
This lets me “play” with values and case sizes and learn from it. It’s also a great way to get use to making custom footprints. You can also switch to a “Hand Solder” pad layout if you think you’ll be trying out different parts.
W/r/t/ filters, “chokes” (1 to 30 uH or so) are good for low frequencies (< 50 MHz), and ferrite is good for higher frequencies (> 50 MHz). The video you have in your 3rd comment addresses this.
Another though: if you have, for example, a 47 uF ceramic, perhaps in a 1206 case, you can solder on a 0805 on top of it to see what a 100, 10, or 1 nF could do for your emissions. If this is a “hobby/personal use” design, it’s easy to just do than manually and not do another layout spin or try to squeeze in another cap.
Hinted at in the TI references is using the bottom layers as a ground plane, and typically the only connections on the bottom (and not underneath any of the high current loop areas) are the feedback to the switcher (with the restore divider right at the switcher). If you can’t work the topology, remember there are 0 ohm “resistors” available. A 1206 or 0805 0 ohm makes a great way to jumper a single and keep your ground plane clean. These are best used on non-power signals.
OK on using JLCPCB, IDK if they have a 2 oz copper option. If JLCPCB can handle 0603 or 0402, you may have some options for getting passives closer to the switching chip by using components of those sizes.
I realize this is a special design- outputting “+ and -” voltages. If at all possible, for simple buck converters I try to use a switcher chip where there is no external snubber diode- the chip has a FET on it. This is more efficient and has less EMI concerns.
A spectrum analyzer is a great tool for al this, but indeed they are not cheap. Conducted measurements are easy and repeatable to make. There is no such thing as a cheap hobby.
Sounds like you’re on your way and what is in the TI sources is more than I can pass on. What you are going through is a right of passage when you start working with switcher designs and layouts.
I know you like JCL, but every switcher chip I’ve worked with I make a small PCB and run it at OSHpark. Often the cost is < $10. It lets me play with the chip so I don’t have to “learn” on whatever the final project is. This also helps develop your soldering skill so you can try things out on your own.
Have fun learning and building and congrats on digging up the information you need ! (teach a person to fish vs. give a person a fish)
Hi, thanks for showing some interest I worked on the project during the christmas vacation. Now I’m back to my busy day work (software engineering). I definitely need to re-start working on it. And hopefully, I’ll be able to test the various layouts.
Upload away.
