Hi!
I want to ask the community if my design of the SDIO and USB bus looks fine. Previously, I was using a dev board (BlackPill STM32) to write data to an SD card, but I encountered some problems during the communication stage, where the SDIO protocol starts sending data at a 24 MHz frequency. After researching this issue, I noticed that some people suggest it might be caused by incorrect SDIO bus design, specifically related to impedance and trace length control.
To address this, I redesigned the PCB. It consists of four layers, with the top and bottom as signal layers, and the two middle layers as GND and VCC(they are not displayed). I hope you can take a look and provide some feedback, whether good or bad.
Don’t switch layers with you USB traces (and have a solid ground plane below) and make your SDIO traces short and not wiggly. It doesn’t matter if the trace lengths differ by a couple of milimeters
Yes, as always, a properly designed GND plane is the first thing to add, unless this is a 4 layer board with GND on internal layers and rendering for this is just turned off.
And why are you using such extremely wide tracks? Wide tracks for low current digital signals have no benefit, but they add capacitance (especially to a GND plane if that exists). I use a default of 0.25mm (10mil) That track width is already capable of handling 500mA. A lot of PCB manufacturers can make thinner tracks reliably, but sometimes at a higher cost (One of the reasons that 4-layer PCB’s are more expensive is because often another process line is used with a higher resolution). With 0.25mm tracks, you hardly have to think about whether your PCB manufacturer can make it.
In such design at each point where fast signal track jumps from top to bottom the GND and VCC planes should be connected with capacitor as close to changing layer point as possible to let return current a way to jump from GND to VCC plane.
This is 4 layer but not having both internal layers being GND.
If OP will change it to have both internal layers GND than near fast signal jumping from top to bottom internal layers should be connected with via as return current always travels the nearest plane.
