Der Routing-Startpunkt verstößt gegen DRC,The routing start point violates DRC

Well, I correctly guessed German. (Firefox doesn’t auto-detect, :frowning: )
Please translate BEFORE posting if possible. Thanks.

Hi,
ich habe ein Problem:
Ich habe 5 SMD-Pads gebaut.
Habe den Schaltplan correct mit den Pads verbunden.dann habe ich den Leiterplatteneditor gestartet und das PAD gesetzt.
Wenn ich jetzt eine Leiterbahn(rot) legen will kommt dasBild 3

Hi,
I have a problem:
I have built 5 SMD pads.
Connected the circuit diagram correctly to the pads.then I started the PCB editor and set the PAD.
If I now want to put a trace(red) the picture comes 3

und die Message"Der Routing -Startpunkt verstößt gegen DRC.Was tun.
Da ich kein englisches Kicad benutze kann ich mit den vorgeschlagenen Topics nicht anfangen.
Danke.

and the message"The routing start point violates DRC.What to do.
Since I don’t use an English Kicad, I can’t do anyway with the proposed topics.
Thank you.

Gruß
Reinhold

Looks like there is a big pad (in green) sitting on another pad.
That’s likely to cause DRC errors.

Hi 3Dogs,

it looks like. The green PAD is only the message from the DRC.
I had a view into the footprint. There is only the red layer, nothing else, except the name and position.

That message is quite self explanatory for me, and therefore I am guessing why you are having problems with it. I also do not know what sort of object the highlighted green rectangle is. I assume it is a pad.

If pads of two different nets are for some reason stacked on top of each other, then you can not draw a track from such a pad, because that would violate the DRC rules (I.e. short the two pads together). KiCad does not do DRC checking during movements of footprints (or tracks or blocks, etc), but it does do real-time DRC checking during drawing of tracks. (I assume you know what DRC is).

Dear guys,
thank you for your help. I found the reason. The reference in the footprint properties has the wrong layer.
The SMD PAD was imported/converted from eagle.
To change the layer from F.cu to F.fab solved the problem. see the below image.

br Reinhold

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