I was preparing another topic about that point on the forum
But as you mention it now, I will present my point here:
In the KiCAD Design Rules, it is written Via drill… So if I understand well, this is incorrect and it should be named Via hole instead.
Because, as you explain, that value from the design rules will be the finished hole size, and not the drill size (for a PTH, the drill size is larger than the finished hole size).
So, is it sensible to ask KiCAD to change the term Via drill into Via hole in the design rules panel?
Most people in the pcb industry will understand via drill and via hole as synonymous. Remember that many of us are not native English speakers.
And even in my mother tongue I have talked about via hole before plating and via hole after plating with a manufacturer.
We should try to be precise or, at least, avoid inconsistencies.
If a value is called “via drill” in KiCAD, but is not the actual size that the manufacturer will drill, this is an inconsistency.
That is why the term “via hole” is preferable, I think.
PS: Examples of definitions from a manufacturer, explainting the concepts that I am talking about.
I agree with you 100% on this one. PCB designers should not be concerned with what tools the manufacturer uses, but just with the end result, which is “via hole size” (or any hole size in the PCB).
I’ve found other inconsistensies like this that sent me off on a wild goose chase, but applying common sense normally solves the issue.
The multi-lingual nature of the KiCAD Team can give rise to this kind of thing, but on the other hand also gives opportunities for multi-lingual versions and support, which is a good thing.
Don’t forget, it’s open, free and largely based on volunteer work.
I’m not sure that hiring a “Chief Editor” is possible.
For PCB’s you do not want to drill the whole width of the track away. Therefore the copper rings are also a part of the via. They should be big enough that even with tolerances in hole placement the full circle remains intact. (This also makes sense).
Yes, the circle (or square in der.ule’s 3D drawing) should be of great enough diameter to equal the diameter of the track to which it will be attached. Hopefully enough “artificial intelligence” is built into
kicad to figure out what that diameter is. Otherwise the fabricator might have to fill in gaps with solder.
In verying degrees, I speak 6 languages (English is my native lang) - others who speak several languages experience a ‘same phenomena’ which is best exemplified in this TED Talk and, when recognizing this, it’s, both Understandable (and excusable) why confusion results.
I don’t know about recent version releases of FreeCAD but, in early versions, “Tesselation” meant different things to the different Plugin coders yet, they still used the same word…
The PCB manufacturer drill the via a bit bigger than the specified “Via Hole size”. Together with the copper you will get the specified “Via Hole Size”
I see a gold ring surrounded by a yellow ring surrounded by a green ring, in order of increasing diameters. I understand that the drill will drill out a hole of diameter B, show by the black dotted circle.
I understand that the inner gold ring is the plated part of “plated through-hole” (added after drilling the hole). I understand that the green ring is just the extent of solder mask that will surround the hole.
I deduce that the yellow ring is just that part of the PCB between the plating and the solder mask, which is unprocessed. ( I think this part of the PCB is called “the courtyard”.) Do I understand this correctly ?
Almost
The light yellow ring (dia C) isn’t part of the plating and soldermask, this is the plating. This is the annular ring. There must always be some copper that the fabricator drills through.
There will not be any courtyard here. Courtyard is a safety border around components to ensure that a card can be populated because if components are too close they cannot be placed. Via’s do not have courtyards as they are fabricated not assembled
I further deduce that at the board’s surface, the plating extends farther away from the drill centerline than it does below the board’s surface.
Thank you, Naib.
Exactly.
The Via is meant to route signals to other layers via a piece of copper
There are two key pieces of information when creating a via
Annular ring
Via diameter
When a PCB is made it goes through a few steps
Print your artwork onto the copper laminate
Etch the copper laminate to leave behind your desired shapes. Repeat for all layers
Bond all layers together
DRILL plated holes
PLATE
DRILL non-plated holes
apply mask
apply silkscreen
Now because a via is plated with copper, the drill must be larger than the finished via (NOTE: always quote finished diameter to a fab house). So since the drill diameter > hole diameter, the starting circular shape on the PCB must be larger than the drill bit used. Not only that, drilling is not perfect (damn accurate but not perfect) and the drill is never exactly centre to the starting circular shape. This is why the “Annular ring” (because what is left after drilling is a ring) must always be larger than not only the finished via, but also their drill size. This is also why it is always recommended to include TEARDROPS on PTH to ensure that if a misalign occurs, it does not break contact with any traces leaving a via
Sounds complicated. Your 3-D picture helps, Naib. It seems to imply that even if a via is routed to copper plane y, it might NOT be connected to plane y electrically, depending on how the manufacturer processes the PCB. That is certainly an important thing to know for the person who populates the PCB.
EDIT:
The photographs showing how EAGLE makes teardrop shapes at vias is important and helpful. Thank you, Naib. Now I understand why teardrop shapes at vias is important and helpful.
No. It’s dependent on your design file. What Naib shows is a multi-layer PCB where you don’t necessarily want to connect every layer through a via, although the via passes through all layers. That’s what the “anti-pad” means. But it’s defined in your design file and has nothing to do with manufacturer processing.
The other way of solving this issue is using “buried vias”, but that’s significantly more expensive.
