What are “Via Size” and “Via Drill” diameters in the NETCLASS definition?
I understand “Via Drill”: it is the diameter of the drilled hole.
But what is the “Via Size”?
A sensible definition would be: “Via Size” is the finished hole size.
For a PTH, the finished hole size is smaller than the drill size, because of the plating inside the hole. For a NPTH, the finished hole size is equal to the drill size, because no other material comes into the hole. But, KiCAD complains when the “via drill” has a value larger or equal than the “via size”.
So, the sensible definition does not work… So what the hell is the definition of “Via Size” ???
If you view the board in the 3Dviewer, and turn of the board and some of the outer layers such as the solder mask, you can look into the board and get a pretty good idea of what it all looks like.
Is there a confusion between the terme “via” and “via pad”?
They are quite different things:
“Via” = plated hole
“Via pad” = copper shapes on the top/bottom/inner copper layers, that surround and connect to the via
For PCB’s you do not want to drill the whole width of the track away. Therefore the copper rings are also a part of the via. They should be big enough that even with tolerances in hole placement the full circle remains intact. (This also makes sense).
So, a via is different in chip design than in PCB design…
OK, it is an important difference for me to know, thank you.
vias (…) it is much smaller than a PTH
That phrase is slightly confusing, because PTH are used for every via that goes throughout the board. The “VIA” that you point at on your draw is using a PTH. The other one is also a PTH, but for THT mounting.
The same concern happens in chip design: it is necessary to take into account the tolerance of the registration between the different layers.
However, even if the concern is the same in both fields, the term “via” is only used for the vertical structure in chip design.
Both approches make sense. From a linguistic point of view, I prefer the definition in chip design. But if I do PCB design, I can take the corresponding defintion.
Terminology/jargon between different industries (even industries as adjacent as PCB design and as I’m learning chip fabrication) may use the same term for subtly different things. But as it is said, the devil is in the details. In PCB design the via includes all parts of moving a signal from one layer to another. Not only is this the hole, but the plating in the hole and the round copper rings for traces to connect to. I’ve never done chip designing/fabrication so all I know about it is what you’ve explained above, needless to say it seems like it is a more narrow definition. To help you out getting into PCB design, here are a few terms that you may run into:
Annular ring - This is the ring of copper around a hole, also sometimes loosely referred to as a pad. This measurement is from the edge of the finished hole (this also includes the thickness of the plating) to the nearest outer edge of the copper ring.
PTH - Plated Through Hole. This is a hole in a PCB that has the walls of the hole plated by the manufacturer. Most often this is to pass an electrical signal or power. When specifying a PTH hole to a board house, the value used is the finished hole size. The manufacturer will then use a slightly larger drill to make the hole based on the plating thickness that they use. Except for very rare cases the PCB designer has no control over the plating thickness and the board house just plates to their internal SOP which hopefully conforms to or is driven by relevant industry standards. This includes both vias and component pin holes for multilayer boards.
NPTH - Non-Plated Through Hole. As the name suggests this is a hole in the board that has no plating on the walls of the hole. Usually these are mechanical holes (registration pins on components, PCB mounting holes, wire routing holes, etc). Again, the hole specified is the finished hole size, but because there isn’t any plating the manufacturer will/should use a drill bit matched to the specified hole size. For a singled layer board all the holes will be NPTH because for the plating process the manufacturer needs copper on both sides.
When looking at manufacturer specs and translating to sizes in KiCad, know that KiCad doesn’t directly specify the annular ring size. In KiCad you specify the total diameter of the pad and the diameter of the hole drilled in the pad (usually the middle, but not necessarily always). The annular ring size for a drill centered in a pad then would be (pad diameter - hole diameter) / 2. Adjust the formula appropriately for non-round pads to find the minimum annular ring size.
I was preparing another topic about that point on the forum
But as you mention it now, I will present my point here:
In the KiCAD Design Rules, it is written Via drill… So if I understand well, this is incorrect and it should be named Via hole instead.
Because, as you explain, that value from the design rules will be the finished hole size, and not the drill size (for a PTH, the drill size is larger than the finished hole size).
So, is it sensible to ask KiCAD to change the term Via drill into Via hole in the design rules panel?
Most people in the pcb industry will understand via drill and via hole as synonymous. Remember that many of us are not native English speakers.
And even in my mother tongue I have talked about via hole before plating and via hole after plating with a manufacturer.
We should try to be precise or, at least, avoid inconsistencies.
If a value is called “via drill” in KiCAD, but is not the actual size that the manufacturer will drill, this is an inconsistency.
That is why the term “via hole” is preferable, I think.
PS: Examples of definitions from a manufacturer, explainting the concepts that I am talking about.
I agree with you 100% on this one. PCB designers should not be concerned with what tools the manufacturer uses, but just with the end result, which is “via hole size” (or any hole size in the PCB).
I’ve found other inconsistensies like this that sent me off on a wild goose chase, but applying common sense normally solves the issue.
The multi-lingual nature of the KiCAD Team can give rise to this kind of thing, but on the other hand also gives opportunities for multi-lingual versions and support, which is a good thing.
Don’t forget, it’s open, free and largely based on volunteer work.
I’m not sure that hiring a “Chief Editor” is possible.
For PCB’s you do not want to drill the whole width of the track away. Therefore the copper rings are also a part of the via. They should be big enough that even with tolerances in hole placement the full circle remains intact. (This also makes sense).
Yes, the circle (or square in der.ule’s 3D drawing) should be of great enough diameter to equal the diameter of the track to which it will be attached. Hopefully enough “artificial intelligence” is built into
kicad to figure out what that diameter is. Otherwise the fabricator might have to fill in gaps with solder.
In verying degrees, I speak 6 languages (English is my native lang) - others who speak several languages experience a ‘same phenomena’ which is best exemplified in this TED Talk and, when recognizing this, it’s, both Understandable (and excusable) why confusion results.
I don’t know about recent version releases of FreeCAD but, in early versions, “Tesselation” meant different things to the different Plugin coders yet, they still used the same word…
