Hello everyone:
I am making a design with USB2422 from Microchip. I assign the footprint: Package_DFN_QFN:QFN-24-1EP_4x4mm_P0.5mm_EP2.6x2.6mm_ThermalVias
When i do the DRC i found 9 errors related than the default thermal vias are of 0.2mm and this raise the price. But if i rise the diameter to 0.3mm the problem is that the component does not match with the library and get a warning.
Maybe kicad require both footprints, with 0.2mm and with 0.3mm or only 0.3mm.
Thanks for everyone
You can create your own library, copy the footprint you need into it, rename it, modify it, and use it in your projects to avoid the warning that the footprint does not match the library.
The reason for this is to reduce solder theft by the via. You can go up to 0.3 mm, but no larger or all of the paste will be gone. See the post above for the method.
I know this even i can create from scratch or find on snapeda. But i think that the main idea of built in footprints on kicad librares is make the work more easy.
My post was a suggestion to fix the library, if dont, there is no problem from my part
Fix for whom?
I ask because this doesn’t appear to be a generic footprint issue but instead a wider PWB consideration.
I wouldn’t be able to use 0.2mm via since my standard thickness is 2.4mm (even for 6layer cards 
) and 0.2mm exceed the recomended aspect ratio. Other people however will be working with 1.6 and lower boards where 0.2mm could be the standard.
as @davidsrsb stated, there is solder theft to consider and I posted on this forum where 0.3mm wicked the solder away so I would say 0.3mm is too high for a via placed in a pad but not treated as a true “via in pad”.
Some designers will use 0.3 mm, or even more for a thick board, but will fill or plug the holes to avoid the solder loss. This is a fairly expensive extra process step.
There is no one size fits all.
Is easy in a PC with a CAD mark an hole with 0.2, or even 0.1. But this is not a trivial thing because not all manufacturer has 0.2mm capability, of if have it the PCB raise the category multiplying the cost x2 or x3.
I have not done a QFN myself yet, but from what I’ve read this works:
My understanding of how this works during soldering, is that the small blobs of solder / flux will each melt and form a good thermal connection between the IC and the copper pad. Both the channels between the solder blobs and the via’s create room for excessive flux and solder to move away, so it does not get trapped under the IC.
And as far as I know, solder wicking into the via’s is not a (big) problem here, because the gap between the bottom of the QFN and the copper on the PCB is narrower, and has stronger capillary action.
For home soldering, sometimes a very big THT pad is placed in the center of the QFN. Then some paste is applied, and the whole combination is heated by poking a soldering iron though the hole from the underside of the PCB.
When i live in argentina i only have 0.5mm as minimum hole. As you said i have no problem with the QFN, is more possible have a problem with a regular pin. Because the accelerometer that i use with QFN has the pins a 0.1 mm more inner than resin, so you need a llitle more of stain on the pins to get contact. Bue never a problem with 0.5 on central pad.
A 0.5mm hole will steal significant amounts of solder. One trick I have seen done for hand assembly is to use a much larger single hole under the exposed pad, maybe 3mm, and hand solder through it after the reflow. Messy, but electrically and thermally effective.