Decoupling power



I am working on a small pcb design that still has quite a few decoupling capacitors. When doing the layout I end up with one big power net (3v3 in my case) and a lot of caps that need to be attached to ground (and on the right place).

I now need to use my brain for DRC is there a way to make this easy? I think would like to have the equivalent of a 0 Ohm resistor trace so the connected pin and the caps are on the same net. is there a solution for this?


Not yet, I’m working on it though.

For the time being, I’d probably put a resistor into the schematic to separate the nets, do the layout for the capacitor, then remove the resistor from the schematic and update the PCB.


It might be better to use the net tie symbols and footprints instead of using a resistor.


The idea is to remove the footprints once the capacitors are placed and wired up. The net tie footprints are meant to stay in place, which is fine for things like connecting power nets, but takes up too much space near the IC usually.


Is the REAL question,

“How can I tell KiCAD that a particular component (probably a decoupling capacitor) is associated with a specific component pin and should be placed near that pin?”



I know. I’m working on that, but I don’t have a lot of time, so it will be a while until I get that working…


If I understand correctly the idea would be to add meta-data to the schematics that the capacitors are for decoupling and therefore need to be as close as possible to the component they are attached to?

Pherhaps by drawing a box around the bypass component and adding meta -data?


or maybe a flag for decoupling cap & IC pin… like those power flags…


Generally, yes, by putting notes in the schematic. Or by how you draw the schematic. I hope you aren’t trying to do layout without the schematic next to you.

One technique that I use on my schematics to help communicate bypass capacitors is to have the power pins for my ICs on separate units/gates. And put the decoupling capacitors next to the power unit of the IC. Something like what is on this schematic: I&O_Expander_Schematic_v2.0.3.pdf (192.2 KB)

For location critical other components (timing parts, noise sensitive biasing parts, filtering parts, etc) I would have to make do with notes on the schematic that I would read while doing the layout.


Whether it’s your personal habit, or the “house rules” where you work, practices like this can be helpful. But in the end, the guy doing the layout must have some knowledge about the overall design and apply his intelligence as he converts that design to real hardware. The day may come when the layout guy (or gal) is reduced to being an appliance operator who clicks on a prompt and the software takes over. but I think that’s unlikely to happen any time soon. Just look at autorouting: it’s been around for 30 or 40 years, but it’s not widely used because people are still believed to do a better job.



My usual technique (not KiCAD specific — I used to do that with gEDA as well) is to put meaningful reference to the capacitors. For example, for simple ICs that only have one Vdd and one GND, if the chip is U3, then its decoupling capacitor is CU3; if I have, say, an MCU or a DSP chip, or some 48 or 64 or whatever many pins, then I number the capacitor with the pin number it decouples. For example, if I have a DSP chip, then I label its decoupling capacitors CD? (D for DSP); then, if pins 5, 13, and 21 require decoupling, then those capacitors will be CD5, CD13, and CD21.

For common power source decoupling — e.g., decoupling the output of a DC/DC on-board power supply, I just label those CP5, or CP3 (P for power, 5 for 5V, 3 for 3.3V, and I add M as needed — M for minus with negative voltages). The additional “bulk” capacitor, well, that one is obvious: CB5, CB3, etc.

I agree that it would be great if the software provided some assistance — @GyrosGeier, I look forward to your solution!


The general idea is to add an annotation to the capacitor to place it close to a particular pin, this would then generate a net tie during netlist generation, so you end up with a ratsnest that tells you which capacitor belongs where.


Will there also be something on the schematic to show the association between the capacitor and its associated pin?

Will the net tie:

  • Be placed between the capacitor and its associated pin, or . . . .

  • Will the (capacitor plus associated pin) become a two-node net, with the net tie linking this to the larger net ?

Either way, I suppose somebody will complain about “all of those net ties cluttering up the board”. And, on a dense or crowded board, the designer has the added task of deleting each net tie and replacing it with a short, direct, connecting trace. (If the layout is spacious the net ties can probably be left in-place.)

From the perspective of the layout guy who is tasked with placing those parts in close proximity, would it be equally effective to simply show the association with a ratsnest line of contrasting color, rather than adding additional components? (Or perhaps a line of a different style - dashed, dot-dash, etc.)

Decoupling capacitors aren’t the only parts with proximity constraints. Two components may require close proximity to enhance thermal tracking, even though they may not share an electrical connection. Or . . . a component may require separation from another component to avoid thermal coupling. Similar requirements may exist when a component is susceptible to, or a source of, electrical noise. Are there creative minds on the Forum who can suggest an approach that could be applied to these other cases, as well as the case of a decoupling capacitor and its associated pin?

(Currently my personal approach is to draw graphic lines around the affected symbols on the schematic, and add a numbered “Note” .)



The net tie will be placed so that the capacitor and the power pin form a net (so they get a ratsnest line, always), and that net needs to be connected to the rail in one point.

Net ties can be combined with vias or pads if desired, so they don’t necessarily use board space (otherwise I’d be happy with the current net-ties-as-components approach). For the decoupling capacitor case, you’d drop the net tie on the pad of the capacitor or on the via to the supply plane, whichever makes more sense.

The function of the net tie is to allow multiple nets to be connected to the same point, which requires a new first-level object in any case, the option to collapse it with vias and pads is fairly cheap compared to that.


@GyrosGeier, is there an issue in launchpad related to this work so I can track it? I guess it would be available in the v6 release and not in v5.x?


I’m planning to get it into 6.0, but it depends on how much time I find to actually implement it.

The current state usually lives in my git repo on launchpad. I’m focusing on the PCB side for now, in features/net_ties/pcb, and I’m going to see what can be salvaged from the schematic and netlist code after that (there were major changes in eeschema, and my old net_ties branch no longer merges).

The stuff that exists so far is mostly about getting the initial tool up and running, then load/save support, then I’ll take a look at netlist import again.


I’m planning to get it into 6.0, but it depends on how much time I
find to actually implement it.

I really hope you can get it in time!

Some time ago I routed a board that had a clock buffer. This IC needed
two decoupling capacitors in each power input (if manufacturer says, I
do it). This improvements you are implementing will support cases like
this? Where the IC pins need more than one footprint nearby?


Just a heads up: v6 is still quite some time away. The next release will be 5.1 early next year. My personal guess is that v6 will be two years after the release of 5.1 (Unless kicad gets a massive boost in resources.)