Hi all,
I am new to KiCad and PCB design in general and currently designing my first board. As far as I have read, the placement of an IC’s decoupling caps is crucial for a correct functuality. So, I am designing a low-noise amplifier based on the AD8429. The datasheet (https://www.analog.com/media/en/technical-documentation/data-sheets/ad8429.pdf) proposes to place a smaller 0.1 µF cap very close the the IC’s power pins and another larger 10 µF cap that can be farther away. I have already found a lot of information about the placement of the smaller 0.1µF cap, so I placed it very close to the IC’s pins as recommended and added a couple of vias also very close to the capacitor’s pad. I further placed the 10 µF cap on the other side of the board since space is very limited on mine. I connected it from the 0.1µF cap while the leads of the 10 µF caps are directly connected to ground and power plane of my board (4-layer board: sig-gnd-pwr-sig).
It would be awesome if you could check whether the placement of the vias and the caps and their connection is reasonable. If not, I’d be very happy to hear your recommendations!
The capacitor is basically just a small, fast acting battery that helps prevent dips in the voltage. That’s why you want them close by the pins. That said, we try and limit out discussion here to things a little more related to using the software and not design questions. EEVblog is one of the larger ones where you can get plenty of input like this. I’d say join that one for design questions and stop by here when you have problems translating the design using Kicad. Make sense? Good to have you on board.
I have been designing power supplies for > 40 years and I think your attention to these details is very sound. I like your layout but I have one question:
Why are you using a radial leaded electrolytic capacitor for C2? It might be OK, but tantalums and electrolytics have more ESR than ceramics do. Why not use an 0805 or 1206 size (X5R or X7R) ceramic for C2? Having some electrolytics (with their ESR) somewhere is useful for damping resonance. But that can be even more C, and does not need to be so intimate with the IC.
I am also not sure why you’d use an electrolytic capacitor for just 10uF. You can get basic SMT ceramic capacitors in that capacity no problem. Electrolytic capacitors use more space, have a higher ESR, are less durable and heat resistant, and are probably more expensive. THT components especially are also expensive to solder in mass production.
That is indeed a good question. Honestly, I had a reference board using electrolytic capacitors, so I thought it would be the way to do it. But I just looked up that also capacitors of this size are easily available as ceramic capacitors which is great because it solves my space problem, so thanks a lot for pointing this out! My desing now looks like this:
That’s a pricey little in-amp. If you are trying to get close to its very-low noise performance you need to kick up the gain, making the layout more critical. If you are needing super cmrr you want to keep the +/- input trace routes as balanced as possible (and close together to pick up the same external noise fields).
In addition to the previous advice of changing to ceramic 10uF caps, don’t use a low-voltage ceramic or its value will drop due to dc bias (eg: a 10uF 6.3V ceramic may only be a few uF at 5V dc). In 0805, 50V ceramics are cheap and plentiful at 10uF (no so much as value goes up). In 0603, 10V 10uF is more common and better for coupling.
Flood-fill ground on the top also (or at least bond the pos/neg cap grounds together on the top vertically down the middle of the chip).
Another option for sensitive input traces is to drop them down to layer 3, and use layer 4 for mostly-ground, fat power traces, and misc bottom parts with minimal signal traces. Then you can have those layer-3 signals surrounded by ground above and below. It is also a good way to contain noisy signals to keep radiation down for emi emissions.
Thanks a lot for your advice! My application is Magnetic Particle Imaging (MPI) which is a new imaging technique comparable to MRI. This device needs a low-noise amplifier since the measured signal is very small (~µV).
Interesting application! I design eeg systems – also signals down to about 1uV. In addition to low-noise design, cancelling powerline noise is a major challenge. Differential adc is needed to subtract non-signal noise reference (plus lots of dsp number crunching).
Thanks a lot, I will look into it! Yes, it is challenging for a first PCB… but EEG design sounds also pretty interesting! I like all applications in the medical field, it is a quite rewarding work!
Not sure if it is important in your application but when you connect parallel two ceramic capacitors with different capacity you get rezonanse between them at some frequency (between minimum impedance point of one and second). At that frequency you are losing the blocking performance.
That effect is not important when the bigger one is tantalum or electrolytic because of their higher ESR. Just do some simulations using capacitor models including parasitic elements.
