DDR3 layout requirement?


#1

Dear Kicad Members,

Does anyone know any information about DDR3 layout requirements ?
If I have 32 bits CPU, and using 2 x 16bits DDR3,
the configuration will be lower data bits 0-15 to the first DDR3 chip,
and upper data bits 16-31 to the second DDR3 chip ?

Thanks


#2

Your diving in the deep end here, but here are a few references.

All of this you will have to layout by hand, you need to match lengths, avoid cross talk between lanes, and maintain a constant impedance,




#3

Thanks for that,
Ok, I will route it manually on that part, can it be mixed between manual and auto route ?
And another question,
Why D0-D15 on RAM chip side are not in the same order with D0-D15 on CPU chip side.
CPU = 32 bits, RAM = 2 x 16 bit.
I’m thinking RAM D0-D15 = CPU D0-D15 and RAM D16-D31= CPU = D16-D31 ?


#4

Thanks for that,
Ok, I will route it manually on that part, can it be mixed between manual
and auto route ?
And another question,
Why D0-D15 on RAM chip side are not in the same order with D0-D15 on CPU
chip side.
CPU = 32 bits, RAM = 2 x 16 bit.
I’m thinking RAM D0-D15 = CPU D0-D15 and RAM D16-D31= CPU = D16-D31 ?


#5

Could you please have a look on the capture I had made ?
Thanks


#6

Could you please have a look on the capture I had made ?
Thanks


#7

From what i can find there is no issue with swapping lanes so long as high and low are not swapped.

I would strongly insist you route high speed nets by hand only. Your dealing with very high frequency, crosstalk sensitive, controlled impedance and skew signals.


#8

I see, I will route it by hand, how many layers do I need for 350 pins BGA meets with 96 pins,
would 8 layers be enough?

Thanks


#9

From I can see DQL0 chip 1 = SDQ3 and DQL0 chip = SDQ20, there’s 16 bits gap,
and it’s not in order, is it right ?


#10

Link to the schematic, I know its an orangepi project, and having the proper part numbers is the only way i can answer that.

At a guess 4 if your a pro, 6 if your good, 8 if you want it easy.


#11

for an idea on how to route it, take a look at page 9,


#12

Ok, Had a better look at that Allwinners pinout, and i would say definitely on 4-6 layer. Almost all the center is taken up by the grounds and power planes, meaning you have your decoupling on the far side and happy days. Leaving you with roughly 4 balls deep at any point around the chip with plenty of missing pads to allow for some routing cleverness. which would be only 2 signal layers to escape. e.g. on a 4 layer, Signal - GND - GND / Plane - Signal. you would just make sure on the 4th your signals had a clear ground return path.

A part of me feels tempted to try and fan out this BGA on 1 signal layer, but I’m going to have to call it a night. Its so much easier at 4/4 rule.


#13

I prefer taking it easy, 8 layers, reducing the difficulities and headache.
Anyway, I have the board with me but can not boot, do you have an idea why ?
Yes it is Opi.
The Power LED can not on at all, it’s quirky ?
I’m using 5V ATX power supply, so the power should be sufficient,
my DevBoard is Opi Lite.


#14

Part number is :
K4B4G1646D-BCK0

It’s
DDR3-1600 (11-11-11) , 256Mx 16, Samsung 4Gb DDR3 D-die

Any clues or experiences ?