Hello, I meet a strange error message in a schematic Darlington connection, I put the emitter of the first transistor to the base of the final transistor, the system shows me the following message:
Error:Input pin not driven by any Output pin.
I resolved putting a 0 ohm resistor between the emitter and the base.
For me is very strange solution, what you thing about?
Which symbols do you use?
Pins have different designations for the purpouse of electrical rule checks (ERC), and apparently the symbols have incompatible pin designations for this kind of connection. Apparently the base is designated input but the emitter of the other transistor is not an output.
Two random transistors I checked (BC817 and BD140) have base designated input while collector and emitter are both designated passive.
You can ignore the ERC message or edit the symbol to change the appropriate pin, for example emitter of the first transistor to output.
You don’t need too look for a symbol with passive pins as this is something you can change on a temporary basis for this project or create your own dedicated symbol and lastly I believe the Kicad library’s have a symbol for the Darlington configuration anyway
I think that any darlington symbol probably represents an integrated darlington (with two BJTs on one chip or at least in one package) while I think the OP is describing two discrete transistors.
Unless the two “Oh, my Darlington!” transistors are doing something indiscreet.
Not sure why the base is given type Input. Lots of situations where it’s not directly connected to an Output. I don’t come across this anomaly because I use the generic transistors under Device where all the pins are Passive.
At least in general terms (maybe not our ERC rules) the base of a BJT is almost always an input. The only exception I can think of is a common base connection which is not the most um…common.
But even in the case of a common collector or common emitter connection there is likely to be some impedance between the transistor base and a signal which drives it. I am not sure if that breaks the ERC rules.
I think I have encountered ERC issues when I placed an RC filter between the Vcc pin of an IC and the rail that is powering it. ERC then complains that the power input pin is not connected to a power source. (or something like that.) This is an example of where ERC is a nuisance…
And you plan to place it at PCB only to cheat ERC?
So, even others don’t like it, I think my solution is better - I simply don’t run ERC.
I agree. I’m surprised seeing that anyone could decide that base is input. Transistors can be connected in so many unexpected combinations… For example working in common base system transistor base is certainly not an input. All transistor pins should be passive.
Depending on what type of electronics someone works with. I remember in FM heads and TV UHF heads common base was typical. Anyone trying to get from transistors as high band as possible will use common base (for example in cascode amplifier).
On the other hand I don’t understand. I suppose emitter is passive and connected to base (input) is seen by ERC as an error. Then resistor (also passive pins) connected to base is ok?
I just looked through the “Q” list in the Device Library.
All but six of the just over 100 listed have the Base or Gate pin labeled as “Input”. Only three of the possible combinations for NPN BJTs and three of the possible combinations of NPN Darlings have their base listed as Passive.
This used not be the case in past library editions. It seems our librarians have been running amok with the Device Library.
This is not good!
Q_NPN_BCE / BEC / CBE / CEB have B as Input
Q_NPN_EBC / ECB have B as Passive
All six combinations of Q_PNP are Input.
I did another experiment. I changed my generic NPN transistor in a circuit to BC107 and ran ERC and I did not get the warning that OP did although it is listed as one of the checks. I don’t know why. This is for v7.
And come to think of it, how did the 0R satisfy the check? A resistor has 2 passive pins.
I would think many common emitter configurations would not have an Output directly connected to the base, including the classic voltage divider for bias and capacitor for AC signal input.
That’s too much work for me. I’ll stick to strolling amok.
Maybe so, but is that Input/Output ERC check actually applied? Maybe it is only checked for digital gates? As I wrote earlier many common transistor circuit configurations don’t drive Input directly with Output. It’s beyond my pay grade.
I am mostly interested if all my power pins are connected. I once used hierarchial labels for power. And this one time I forgot to connect this hierarchial label to the 5V. So I could fire up the soldering iron that day .
I acknowledge that I am just a human. I am susceptable to making mistakes. I may make a typo in label tags. I can also forget to import a hierarchial sheet pin and thus forget to make a connection. So for me the unconnected warnings are important.
Then there are these carbage messages. I don’t know when or why they start showing up. I suspect it is related to some update?. I also get them from time to time with my own private libraries.
Fact, that I am not using ERC didn’t come form my conscious decision. In far past someone else was designing our PCBs using Protel 3. When CE and EMC came (to us came in 2004) I took it over. I was told how to do everything what is needed and never had a time to read Protel manuals or to look-through all Protel possibilities (what I knew was working for me well). The effect was that since 2004 til 2017 I was designing our PCBs simply didn’t knowing that ERC exists. So when in 2017 I moved to KiCad I was not used to use ERC so simply didn’t used it. From forum I got info that to use ERC you practically have to add PWF_FLAGs to your schematic and I didn’t wanted to destruct my schematics with it. I’m not sure but probably in V5 you couldn’t simply switch off some checks. During V5 I moved all my designs from Protel to KiCad so since V6 I don’t use KiCad intensively.
And directly to the sentence I quoted: All my schematics (in Protel and in KiCad) are single sheet so I have no experience and fear with not connecting something between sheets.
Another feature of my schematics is that they are so simple that when designing PCB connection lines are not abstract for me and I always know what I am now connecting (a kind of having schematic all the time in head).
For more complicated design ERC can certainly be a help to find something what is probably done incorrect.
For me BJT and MOS are separate topics in this aspect. In most cases you can connect digital IC output directly to Gate so it can be understood as input. But connecting digital output directly to Base is in most cases a mistake so Base should not be leveled with digital IC input.
I thought about why I’m not getting Input not driven by Output even when I use a transistor with an Input pin and decided to do a little experiment. Here’s the circuit, the BC107 base is of type Input. Sorry about the cursor crosshair in the middle.
So the presence of other pin type on the bases of Q101 and Q102 disables the check for Input not driven by Output. But the check is applied to Q103 and Q104. That’s how nearly all transistor circuits will not trigger the check, but digital gates will. So it seldom matters that the librarians are running amok, except for the darlington which started this topic. But why didn’t the first emitter connected to the second base inhibit the check? Edit: Maybe the emitter was of type Unspecified and the symbol came from one of those tsk-tsk Internet libraries.