I’m laying out a DDR4 DRAM package which has strict requirements for the difference in routed length between the clock and other signals.
The “skew” parameter in the Custom Design Rules seems the most appropriate, but I want a signed comparison, not the absolute value (i.e. I want to know the result of clock - dqs signal length) as described in the table below.
Is there a way to achieve this with the KiCad custom design rules? I could see adding a condition of (max 0mm) to force a negative sign but I’m not sure in what order A & B get evaluated.
