Custom rule to avoid this type of acid trap

Just got a couple of PCBs delivered that all had the same issue, which looks like an acid trap to me. I might use the wrong term here, so please correct me, but the results are the same.

PCB layout of a differential pair (0.2mm DP Width and DP Gap) entering a SOIC footprint:


See the trace interruption at the arrow and the almost interrupted trace on the other side.
To me this looks like the small spacing between the trace and the pad caused etchant to “hang on”, due to capillary action.

My question:
how can I create a custom design rule that allows me to prevent this or some other method that allows me to flag this? Note that the trace and the pad are from the same net, so minimum clearance settings have no effect.

Latest Kicad (6.0.5).

There’s no way to do it in 6.0. Neither in the current 6.99, but I wonder if it could be possible to implement it. I once asked, in this issue, if something similar could be done with tracks. The same-net checking (“physical_clearance”) actually exists now in the unstable development version 5,99, but I can’t see how it could be applied in a simple way to only nearby tracks and not to the track leaving from the pad.