A question on DRC. I connected 2 tracks (T1, T2) to run a test. See figure. I added T-bridge on purpose to test if the DRC would find the unintended “short” between T1 and T2. Running a DRC does not flag an error or warning.
What is the reason for no DRC flag? I appreciate that sometimes this may be intended but not always. A warning would be nice. Thanks Al (Santa Clara Ca)
Are they the same net or different nets?
All 3 are “no net”. T1 and T2 are just tracks connecting pins on devices not shown.
Is there a schematic? If not that would explain the no net. If the tracks have no net then they will continue to have no net when bridged. But if you had a schematic and they weren’t supposed to be connected then the DRC would report a parity error.
You will need to assign different nets to T1 and T2. Otherwise, there is not enough information for KiCad to guess your intention. Even connecting to different pads or different devices is not sufficient as that is a common (and valid) way of connecting nodes on the same net.
Thanks to retiredfeline and Seth_h,
Makes sense. There a schematic but I didn’t import it for the PCB, so no xcross check against it.
Raises an interesting question. are connections between “no net” and another “no net” treated as if they were both connections to say. Node 52 and Node 52?
Or they more like a “no connect”
from experience: rn no net is considered as a normal net so you can connect every no net object with each other without getting any error. Not to be confused with not connected objects.
EasyPC used to always name nets if not set by user.
i.e. NET00001
As nets were added it would increase net name number
That way you cant miss anything.
Inspired by the discussion above I checked some behaviour i noticed some times ago. It can be understood, that the DRC cannot find this crossing when all nets have the same name. The behaviour sketched by retiredfeline would be OK, but I didn’t notice this in the past. Therefore I sat up a test project:
Schematic:
The schematic is fully annotated and the footprints are assigned. The schematic is transferred to the PCB using the build-in transfer tool. The sample PCB looks like this:
Please attach the zipped test project, as it is in the first situation.
“Melden aller Fehler…” Needs to be checked
Yes, without that checked it will stop after the first error for each track (in this case, the clearance error). If you fix the clearance error it will show the shorting error (even without the checkbox checked, as that will now be the first error for that track).
Unfortunately the clearance error is due to the shortage error: I combine two different nets. If I remove the clearance error, I will remove the shortage and I wouldn’t expect any parity error…
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