Creating thermal via leads to F7.4 violation - incorrect layer settings

I want to create a footprint with thermal vias, so the heat is transferred to the back layer. Those vias should have solder mask, since nothing is soldered there. I created the via with:

  • Pad type: Through-hole
  • Copper layers: -
  • Fabrication property: Heatsink pad

However, the KLC checker gives me a hard time:

 Violating F6.3 - https://klc.kicad.org/footprint/f6/f6.3/
    Pad requirements for SMD footprints
    Pad(s) potentially missing layers
     - Pad '2' missing layer 'Mask'
     - Pad '2' missing layer 'Mask'
     - Pad '2' missing layer 'Paste'
     - Pad '2' missing layer 'Mask'
     - Pad '2' missing layer 'Mask'
  Violating F7.4 - https://klc.kicad.org/footprint/f7/f7.4/
    Pad requirements for THT footprints
    Some THT pads have incorrect layer settings
     - Pad '2' missing layer '*.Mask'

Why are those settings incorrect? I don’t want the solder mask removed on a thermal via. Why is the thermal pad required to have the “Mask” layer set?

How to correctly create thermal vias that satisfy the KLC?


TO-263-2-TEST.kicad_mod (6.7 KB)

Version: 8.0.4+1

Use Vias not THT pads.
Via specifications can be changed in Board Setup > Design Rules > Constraints & Pre-defined Sizes.

Use of solder mask, partially or completely on pad 2, will inhibit the transfer of heat to the top layer pad. This defeats the purpose of vias to transfer heat to the bottom copper layer.

I might be missing the obvious here, but I cannot find a way to place a via in the footprint editor. There’s only an option “Add Pad”. And the property “Heatsink pad” is only available for THT pads.

That’s true for this simple example I posted because the via/pad is under the device in the example footprint, yes. But that was just for demonstration. I’ll be using many more vias on a larger copper area, not just vias/pads under the device.

Sorry, I thought this was PCB. I didn’t read correctly.

Yes use pads to stitch the top and bottom copper layers of pad 2.

I don’t understand what this has to do with pad 2 footprint design.

How to do that without violating F7.4?

I think the checker is just wrong here :person_shrugging: I would ask the library team when you open a MR to add this part.

It does not really work that way. It’s quite logical to want to plug the hole with soldermask, but you can’t print soldermask inside the hole without also printing the soldermask on tne annular ring of the pad, and that makes the pad thicker, and as a result, this influences the soldering of the pad.

The most common solution is to use aperture pads to make several smaller solder paste opening on the pad. This is used in a lot of KiCad’s default footprints. Just search for any footprint with the word “ThermalVias” in it. for example: LFCSP-40-1EP_6x6mm_P0.5mm_EP4.65x4.65mm_ThermalVias

When doing it like this, a lot of sublte things are combined.

  1. Aperture openings are smaller then the pad. This reduces the amount of solderpaste on the pad and thus prevents “floating” of the part on top the footprint during soldering.
  2. The channels provide a way for evaporating flux to escape during soldering.
  3. The separate paste apertures provide a more equally dispensed solder (It won’t wick or flow all to one side).
  4. The holes are covered during paste dispensing, this both reduces the amount of solder on the pad, and makes it more predictable.
  5. The thermal via’s are still open, so excessive solder can wick into it, this also improves thermal conductivity of the thermal via.

And also, over time when DRC gets more complete, more exceptions for special cases have to be made. You can set the Fabrication Property to Heatsink pad inside the pad properties of the THT pad. This is a relatively new feature in KiCad. The user manual is short about it’s explanation:

Pads with the heatsink pad property are always flashed on every copper layer and are allowed in SMD footprints (PTH pads without this property are not allowed in SMD footprints). It also affects Gerber X2 output.

Does that mean that thermal vias can never have soldermask applied? How about this:

I don’t need soldermask removed here.

Ok, the first example with a via on a solder pad was not a good one. What about the case where soldering is not required/desired (see image above)?

That’s what I’ve done (3rd item in the OP).

Exposed copper is better at heat radiation then copper covered by soldermask, but the amount of heatsink copper in your example is very likely much more then needed even without any copper on the other side. My explanation was geared towards thermal via’s inside soldered pads.

I am a bit “sloppy” with reading and often miss such details. It’s not dyslexia, but more a general focusing problem. It’s the main reason I mostly do forum support for KiCad and not programming itself anymore.

I do not want soldermask on pads. That’s for sure. Apologies for the misleading first example. That steered the discussion into the wrong direction. Anyway, thanks for taking the time to reply.

I found something:

Seems like I’m running into this 6-year old bug.

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