Is there any way to specify a courtyard that has holes in it? I have a battery holder that has gaps in it. I want to make use of these gaps to fit some components underneath the holder.
I had these lines defined as a courtyard, but was getting DRC errors complaining that I had things inside it.
I want the large area of this to be the courtyard and the smaller rectangles to be areas where components can still be placed. Any way to achieve this?
Here is the footprint on the board to show some context:
I’m getting the DRC warnings for PTH Inside courtyard for THT pads.
I think I malformed my question now that I look at it again. It looks like the courtyard is actually being used as I would expect (i.e. having things in the smaller rectangles is ok, but elsewhere no).
The 3x3 THT grid on the bottom-left is actually a thermal pad for an SMD component on the other side of the board. Do I have to change this footprint to remove all those thermal vias, and implement the vias in the PCB layout instead in order to avoid these warnings?
Use a different layer, if it’s not on the Courtyard layer DRC won’t complain. You can still see the lines as a guide to where you can place components as long as you have the layer turned on/showing.
I don’t have much experience with the courtyard, but you can try a different strategy.
Draw rectangles (or a polygon?) that only cover the actual area you want to exclude parts from.
Is there any way to specify a courtyard that has holes in it?
Not with the standard courtyard-layer.
workaround in the footprint-definition:
- no courtyard at all (click checkbox for “this FP don’t needs a courtyard”)
- instead place multiple rule-out-areas with “keepout footprints” on all areas where no footprints are allowed
- these rule-out areas should cover all the space except the four inner holes
- drawback: this works only if all other FP have a courtyard. Intersecting two footprints defined with this “rule out area”-method are not recognized!
Maybe there is also a solution with defining only the four inner holes as rule-out area and then additionally write a custom rule which allows footprints inside courtyard in these special 4 areas. (But I’m no “custom rules” expert).
I made a small test to first check my workaround is really working:
R_1206_3216Metric_courtyard.kicad_mod (5.5 KB)
Try using the Silkscreen layer.
The Courtyard layer is for a bounding box showing extents if components so they don’t clash hence why DRC is moaning.
You want, by the sound of it, just a graphic on your PCB
You can switch these DRC errors off.
I have courtyard rectangles drawn at 0.1mm grid and I work with 0.1mm grid placing footprints touching each other with their courtyard rectangles what DRC doesn’t like.
It also happened (one or two times) that I placed a long serie of 600W transils (SMB case) little closer than courtyard rectangles suggested (terminal block (5.08) spacing was smaller than transil spacing and it was the problem).
I also use courtyard for such things like polarity markings for diodes what DRC also doesn’t like. I do it because there is no free user layer pair I could use for it and I want polarity marking at my documentation drawings (where I use courtyard rectangles).
I also have footprints that at PCB are placed over other footprints so courtyards collide (example E core laying at PCB and small PCB with coils inserted at E core legs).
All these made me to switch off courtyard checking by DRC at all.
If you draw the footprint like this
then you can add components in the “holes”.
The “holes” are created as follows
This simple case returns no DRC errors.