The silkscreen is a fairly close approximation of the “interlocking” sections of a terminal block.
(I did these fairly early on, and I could probably make them physically exact at this point in time.)
However, the question then becomes, with the KLC, where does the courtyard then belong?
If you want them to pass the DRC while they are interlocked, then the courtyard needs to be inside silkscreen/fab layer. However, if at the end of a “string” of interlocked terminal blocks, one end will have the protruding male interlock section past the courtyard layer.
At the moment, I think the courtyards in the axis of the interlock should allow for DRC compliance with courtyard interference. The silkscreen, Fab layer, or both, should show the male interlock.
I think the KLC defines the Fab layer for physical obstructions. However, that is not seen by the DRC nor the 3D Viewer.
In my opinion it is easier to make a 4,6 and 8 pin symbol, each with its own courtyard contour than make a discussion of it. I made my own (before KLC even existed) and worked fine.
There will always be cases that can not be represented properly in the KLC. (No matter how complex we make the set of rules for it.)
I this case i would simply draw the exact outline on fab, a larger (but simplified) outline on silk.
The courtyard is more complex. It can not be both used for when there are multiple connectors interlocked or if one is used alone.
So i would draw the courtyard as if these are not interlock able.
The user knows that interlocked connectors can interfere with their courtyard.
This way the outermost outline of the resulting connector courtyard is correct.
If you draw the courtyard such that it does not interfere where the two connectors interlock, the resulting outer outline of the combined connector is missing the clearance on the left and right of the connector.
(You could make 3 footprints. One for the leftmost connector, one for all connectors in the middle plus one for the rightmost connector. But i would say this is a bit much.)
And remember: Neither Silk, Fab or Courtyard are checked by DRC. (There are scripts on this forum where DRC does check silk - copper overlapping but not silk - silk.) And even if it would be checked somehow, the user will know that this is a false alarm.
I think the way described by @pedro is a good option. But it does not allow for a correct BOM and it does not allow for automated assembly. (Only one part in the pos file.) If this is not a concern for you then i would go this route.
The connectors I worked with needed to be interconnected before assembling. We treated them as one 8-pin connector and a one 4-pin connector. Moreover, while placing the footprint on the layout, it was easy to move only one connector instead of 4.
This is not the case in the nightly I have installed; the DRC does check (and catch) Courtyard violations (if the check box to do so is checked).
What about changing the way KiCad looks at Courtyard line widths? Draw the perimeter of the Courtyard with exact values, but if a very wide line width is used it becomes a zone that would interlock with the same other zone? Just stream of consciousness thinking out of the box at the moment.
This “interlocking feature” is a very common characteristic of terminal blocks. At the moment I’m not aware of any other common parts that interlock. However, there is a tendency for things to become modular and interlock with each other.
