So how do I draw a rectangle on the B.Cu layer, to represent the unetched copper on the rear of the board and have two layers for the plated through holes?
If I select the B.Cu layer, then select add graphic polygon and draw the rectangle, it gets placed on the Dwgs.User layer, with no apparent way to move it to the correct layer. I was able to draw a rectangle on the Edge.Cuts layer easily enough, but this doesn’t work on the B.Cu layer.
If I select the rectangle that is already drawn on the Edge.Cuts layer, and attempt to copy and paste it, it only pastes on the Edge.Cuts layer, again with no apparent way to move it to the B.Cu layer.
KiCad is more object oriented, than layer oriented. Lines drawn on Edge.Cuts automatically propagate to all copper layers (and some technical layers). (Later during plotting you can exclude it from certain layers). So you only need to draw the outline on Edge.Cuts.
A Polygon is just for graphic entities. To draw a “rectangle” on a copper layer use Pcbnew / Place / Zone.
KiCad has a lot of built in functionality around zones. For example I usually draw one in the form of a pentagon around the PCB, and then it gets automatically clipped by the graphics on Edge.Cuts layer.
Zones also automatically keep their distance (clearance) from copper tracks of other nets (after re-calculation with B). But for this to work you need a netlist and assign a net to the zone itself, so it knows where to connect to, and what to keep clear of. (And to get a netlist, you need a schematic…).
So then I do not need to put anything on the B.Cu layer to be able to place plated through holes, correct?
If that is correct, then how is it specified that the back surface of the board is a layer of unetched copper?
Or is it best or most correct to use “place zone” to represent the unetched copper surface on the rear of the board?
So then I will need to add a rectangle identical to the board outline to the B.Cu layer, to represent unetched copper on the entire rear surface of the board - is this correct?
Now this might be a problem. Normally you have a copper setback from the board edge.There is a good reason for this - the edge is cut with a mil and not sawn. If the copper extends to the very edge of the board it will also be cut by the milling bit. Copper is ‘sticky’ and will clog up the bit and stop it cutting - and likely break the bit. I expect that the manufacturer will pick up on this and may reject your design or charge extra if you insist. Unsurprisingly, KiCad deals with this automatically in the normal workflow …
You’ll need to use zones, here is a link to their FAQ:
Thanks, I didn’t know this! What is the typical or standard setback that is used? Easy enough to make everything conform to this requirement, now that I know it exists.
Thanks!
Copper setback of 0.2mm to 0.5mm would be fine.
I’ve just been lurking on this thread, but this caught my attention. What is the material you want these 3 boards made in? What, if anything, of the board material requires a unique (to normal FR4) manufacturing process?
Ok, so I appear to have successfully defined the copper ground plane on the rear of the board, selected the F.Cu and B.Cu layers as a pair, and placed a via. Then I moved it into it’s exact proper position and attempted to adjust it to the correct size. But the properties dialog box specifies a “diameter” and “drill” size. Am I correct to assume that the “drill” size is the size of the actual hole, and the “diameter” is a copper area around the edges of the hole (on the two layers that the via connects)? If so, am I further correct that since the copper area around the hole is already defined by the size of the trace on the F.Cu layer and the unetched copper ground plane on the B.Cu layer, the “diameter” can be ignored as long as it is larger than the “drill” size, and that KiCAD will understand what each end of the via is supposed to connect to? Or do I have to do something else in addition, such as set the “diameter” to be equal to the “drill” size? Again, the documentation offers no definition of what “drill” and “diameter” mean.
One board is Rogers RO4350, one is Rogers AD255C, and the FR4 board is .087" or .090" thickness. I haven’t seen anyplace that these board materials can be purchased by an individual in small quantities. In addition to this, the requirement for plated through holes with a flat surface means that there is really no other practical option than to send gerber files off to one of the board houses.
That is correct.
Incorrect, the diameter of the via (the copper outside the hole, known as annular ring) is manufacturer dependent, a conservative size is > 0,15mm, this information is normally provided by the board manufacturer.
From oshpark:
What happens if I violate the annular ring spec?
Generally nothing too bad, but it should be avoided whenever possible.
The annular ring spec accounts for worst-case fabrication tolerances. Since our typical tolerances are below that, the annular ring usually can decrease by 1 mil (0.0254mm) without serious issues. However, issues that do occur from annular ring violations can be very inconsistent and difficult to debug.
https://docs.oshpark.com/submitting-orders/drill-specs/
https://www.multi-circuit-boards.eu/en/pcb-design-aid/drills-throughplating/annular-ring.html
Yes you have it right. But a detail that often trips people up is the drill size. That isn’t actually the size of the drill to use for plated holes. It is the finished hole. (So it would be the drill size for non-plated holes.) The plating on the inside of the hole has a thickness which depends on the process the manufacturer uses. It is up to the manufacturer to know their own process and drill the hole slightly oversized so the plating thickness closes the hole down to the designer’s specified hole size. The diameter specification you are right is for the amount of copper around the via, and the copper around the hole is known as the annular ring. (These are industry terms.) It is important to have a minimum amount of copper around the drill hole to allow for copper to be left all the way around the hole when a slightly larger than specified drill is used, and to account for drill placement tolerances.
Yes, on the back for your board as you have described it, but for the front it depends on the width of the trace the via connects to. If the connecting trace has a thinner width than the drill hole then the via diameter is to enforce that annular ring. If the via is embedded in a copper pour like you want for your bottom side (known as a zone in KiCad) or in a really wide trace, the annular ring won’t show.
Here is a decent explanation about vias that I found searching for “pcb via cross section” on a web search engine:
This will also be affected by the board’s finish that you specify from the manufacturer. The cheaper HASL may leave small “puddles” of solder on the edges of some pads, but since this melts during the soldering process this is usually not a problem for tabs and heatskins. Even IC packages with pads on the bottom of the package often aren’t adversely affected by this. The ENIG process provides an exceptionally flat surface, usually required for BGA packages, LLC packages, or fine pitch packages. This finish detail isn’t normally specified in the Gerbers, rather you usually have to choose this specification on your job order, or a special job file submitted along with the Gerbers. Check with your manufacturer to find how they want you to communicate this requirement for your order.
P.S. Is it me, or does the screenshot that all about circuits uses for their QFN package showing thermal vias look like it’s from KiCad?
I think it is kicad but it seems that it is the old canvas. The pin 1 marker on the silkscreen is very kicad-tly 
I appear to have gotten all of the vias placed correctly. I believe that the next step is going to be saving as or exporting the board layout as gerber files (and the drill file), and double checking everything to ensure that it all properly conforms to spec. But before I do that, I have one additional question: On the F.Cu layer, the traces appear on the screen as outlines (the shapes of the traces appear “empty”, rather than “filled”). Is this the way it is supposed to appear? If not, what will I need to do, to ensure that the traces properly represent solid shapes of copper rather than lines (or “empty outlines”) on the actual boards?
To explain further, I will use this example. A trace that is the shape of a rectangle appears on the F.Cu layer as the outline of the rectangle (the center is empty), rather than the solid filled shape of a rectangle. On the finished board, this trace needs to be a solid rectangle of copper.
Thanks for this useful information! Again, this is something I had never heard of before. I had always thought that a tinned finish was a tinned finish, and was unaware that there was more than one type of tinned finish. For the board that is supposed to be mounted flat against a heatsink, would it be necessary to specify ENIG? Or if HASL is used, would it be sufficient to make the B.Cu groundplane surface flat by placing a piece of fine grit sandpaper on a piece of glass, and sanding the board in a figure-8 pattern? (Obviously the pressure against the board should be distrubuted as evenly as possible, and the process cannot be done aggressively. I also plan to make the mounting surface of the heatsink flat by this same method.) I would imagine that ENIG is more expensive. If it is recommended to use ENIG for the board that will mount to a heatsink (rather than using HASL and sanding it flat), is it possible to specify ENIG on the groundplane surface on the rear of the board, and HASL on the front of the board?
At left of screen you have a serie of switches. One of them is “Show tracks in outline mode.”
2 days ago I have written:
You can see in 3D how your PCB looks like. You can rotate it to see both sides …
I have an overwhelming impression that you read the answers very selectively.
That has no effect, nothing appears to change.
Your impression is incorrect. In multiple places elsewhere on this board, it is stated that the best or most accurate final confirmation that the layers or traces are correct is to view them with a 3rd party tool such as Gerbv. I have not only read what you have written, I have also read through the documentation, and what others elsewhere have written as well. But before save as or export to gerber files and attempting to confirm that everything is properly in spec, I am first trying to confirm if there is anything additional needed with the traces on F.Cu
I suppose it depends on what type of thermal interface you have between the board and the heatsink. The puddles I mentioned aren’t that big and if you are using a thermal pad I would expect it to conform to the shape of the board. Thermal paste might or might not have a problem with the uneven surface. If you are relying on dry contact… Use some sort of thermal interface. I do have to say that I’m no expert with heatsink thermal interfaces, so take any advice I have with a large grain of salt and maybe contact your board manufacturer to see what they suggest.
How much more expensive, I don’t know and probably depends on your manufacturer. Since you are planning on using fairly exotic substrates, the cost difference between HASL and ENIG might just be insignificant compared to the cost of the substrate. Again, this is probably a conversation you should have with your manufacturer. (Usually manufacturers welcome these sorts of detail questions because they don’t want to provide a product that you can’t use…)
Without some serious extra expense of masking one side, I seriously doubt it. I’m not familiar with the process for ENIG, but that “Immersion Gold” part of the acronym leads me to think that the entire board is immersed in a solution that chemically deposits gold to the Nickle surfaces. I do know that HASL immerses the entire board into a vessel of liquid solder applying the solder to exposed copper on all sides of the board.
Did you click on the blue ENIG and HASL of my post? Those are links to the Wikipedia pages giving simple explanations about them.
That is to view the generated gerber files in Gerbv (stands for Gerber View). The 3D view in KiCad is a decent way of reviewing the board before outputting to gerbers. Even if you look at your board in the 3D view, it is still best practice to double check your gerbers in a program like Gerbv (or any of the many gerber viewer programs out there) to make sure that you generated the gerbers correctly. This is one of those measure twice, cut once protocols.
My best guess is that you imported the outlines of the DXF into KiCad.
I forgot to follow up on this fully… I’m not sure I would advise sanding boards. The different metal layers are all really thin and you run the risk of sanding them away. But if you really want to try, take care because solder is really soft and gummy as a metal. It would have at least as much tendency to clog up your sand paper as copper. Maybe wet sanding? (I’ve never tried sanding boards, so I really don’t have any practical experience. Just a gut feeling.)
Still trying to figure out what is going on with the F.Cu traces. I cannot find any way to get them to appear as anything other than outlines. Selecting and right clicking gives me no usable option. “Fill zone” doesn’t do anything, and I don’t see any options to “convert to zone”, or to convert anything to anything else. Upon opening the 3D view, an error pops up saying “board edges not detected”, even though the board outline is properly drawn on the Edge.Cuts layer. The only thing that appears to be displaying properly there are vias and anular rings. The traces on F.Cu and the unetched groundplane on B.Cu only display at a very narrow range of positions as the view is changed, and only display as a series of horizontal lines (I don’t know how else to describe it) rather than solid shapes.
Working backwards, the PDF that was converted to DXF R12 shows the shapes of the traces to be solid, just as they are in the original design file. The DXF R12 does not open in Inkscape. The DXF R12 does import into two other graphic design programs (but is unable to be saved by those programs as a DXF R12 and must be converted into a different file type to save), and both of them show the shapes of the traces as unfilled. One program does not allow me the option to select a fill or stroke width as it does with any other vector graphic. The other program does allow me to select a color and fill the shapes of the traces, but does not allow me to save the result as a DXF R12. In both programs, the DXF R12 opens with both of the extra rectangles (mentioned earlier), demonstrating that they were somehow being added by Inkscape and not KiCAD.
This appears to be the case, that Inkscape removed the fill. But yet there doesn’t appear to be a way to ensure that Inkscape saves the fill, the saved DXF R12 will not reopen or import in Inkscape, and multiple others have stated that a DXF R12 saved with Inkscape will import successfully into KiCAD. I think something is wrong somewhere, but no not know enough of what is supposed to be happening to be able to determine what it is.
I don’t want this to drag the thread off topic here, but I have only given passing thought to this so far, it is a problem to be solved at a later stage of the project. On one of the boards, the dissipation is small and is not a concern. But one board will be required to dissipate a very significant amount of heat. Flatness of the groundplane side of the board, a copper heat block between the board and the heatsink, and the heatsink itself will all be important to maximizing thermal transfer. So sanding will be required for all of these surfaces, it will just have to be done very carefully on the board itself, as you said, the metal there is soft and there isn’t much of it. If done carefully, you’ll know well in advance when the high spots are mostly knocked down and you’re getting close to the copper, it should be pretty easily possible to get it flat for all practical purposes and not hit the copper at all.
To my knowledge, it is generally not considered wise to use thermal compound with large thicknesses to fill gaps, it is a better approach to remove or minimize the gaps and have flat surfaces. There is also the potential issue to be considered of dissimilar metal interaction between the copper block and the aluminum heatsink, and I have not yet investigated what would minimize any interaction and allow efficient heat transfer at the same time. Otherwise, the heatsink will be conservatively oversized, as will the forced air cooling system. The duty cycle will be low, even in prolonged periods of continuous operation, so I don’t expect it to run much beyond warm in the worst case. This will of course be monitored closely in operational testing, and the cooling system modified accordingly if necessary. I expect that the biggest problem will be finding something to apply between the copper heat block and the heatsink to discourage dissimilar metal interaction, that will also provide efficient heat transfer, and is relatively inexpensive and readily obtained. In the US, there is a product called Nolox (if I remember the spelling correctly) which is used in house wiring on connections to the aluminum wire that was used for a period in the 1970’s, it is (or at least was, the last that I knew) readily available and inexpensive, but I do not know how efficient the heat transfer abilities are.