That’s fast to fix. Add words “net tie” to the footprint Keywords.
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Wow that works! Thanks? We must have that instruction written somewhere?
Maybe @JeffYoung can tell if it’s in the official documentation.
We could write an FAQ post. People sometimes ask about something which is conceptually a net tie but they don’t know the term.
Sorry, I don’t have a clue.
I suspect it’s slightly more likely to be in the KiCad Library Conventions doc somewhere…
Net ties are currently quite hacked together in KiCad, as an artifact that originated in that graphics on a copper layer was not detected by DRC. I assume that the “net tie” keywords were hacked in as a temporary measure when DRC became capable of recognizing graphics on copper layers.
I did a search through de documentation, including KLC (Just a simple text search through various documents) and the string “net tie” is not found in there.
I did know about the “net tie” keywords. I’ve read a few times about them on this forum, and a search brings up 50+ results:
https://forum.kicad.info/search?q=net%20tie
Better documentation for net ties is on craftyjon’s todo list:
YeffYoung mentioned that “first class net ties” are pushed to KiCad V7 in:
In this thread eelik posted a snippet from KiCad’s source code which recognizes the “net tie” keyword:
I also looked a bit through: gerber-layer-format-specification-revision-2021-04_en.pdf from Ucamco, and on page 142 there is a mention of an “EtchedComponent”. With (optional) embedded netlists and pad information in Gerber files it’s got all the info in there to do flying probe tests.
I suspected that there might be an issue with my net tie, and I searched FAQ for “net tie” but that did not get it for me. I think I remembered seeing something somewhere about the key word “net tie” and even tried a reference designation of “nettie1” but that did not do it.
If there is some good way to collaborate on an FAQ post I would be happy to contribute and initiate it. But I am 98% certain that whatever I write would benefit from edits by some input from more knowledgeable members of this forum.
I like the “make net-ties first class citizens…” descriptor. As so far as I know, the function has been a “workaround” (one that is widely used in pcb layout tools) for as long as I can remember. In my very limited software wisdom, the idea of including the keywords in the footprint field seems perfectly fine; I suppose that could be extended to languages other than English as need be. To me, this now seems to be less of a workaround than other options I am aware of.
BTW I feel very happy with the idea of putting a net tie into the schematic. It is the documentation realization of (for example) the feedback sense wires for a 200 Amp power supply. You have these 10 mm (guess) diameter ring terminals on the power supply output studs, and they are crimped to some AWG 24 wires for output sense.
That “in 6.0” has been removed in the title in the destination of your link.
I did up vote the github issue though.
It’s an evil, but a nessesery evil. There are a few bugbears of how kicad does them and them becoming “1st class” should improve things.
Right now, I can’t make kelvin connections in a sense resistor footprint. Likewise as they are technically a component, such ties can only go on F.Cu or B.Cu
I do not understand. Here are a couple of mine. One is for a real 4 terminal resistor while the other makes 6 terminals out of a 2 terminal resistor.
BTW the second one is a recommendation from a TT type OARS resistor datasheet.
What naib did in another thread is to use net-ties to make the feedback connections:
I find it hard to believe that an integrated 4 terminal resistor could have a better connection then the much cheaper 2 wire resistor, provided that the connections to the pads are made properly as in the picture above.
[Edit:]
I think it’s part “tradition” from the days of THT resistors. The Kelvin connections became a thing back then, and as long as people keep ordering them, manufacturers will keep making them.
I do have to agree with RobZ’s remark below that parameters in a bought 4-terminal resistor could be more tightly controlled than a solder connection. But how much resistance could there possibly be over the width of an SMT pad combined with both the solder and the metalization of the resistor itself? Maybe it has some advantages for extremely low tempco resistors. Maybe it’s mostly for “habit” and “ease of mind”.
I even saw a video of a teardown with some $$$ equipment which had the four terminal connections on the resistor, but they were just shorted together on the pads. I think it was a Keithley instument and I saw it on EEVblog, but details are vague.
OK…so it sounds like a question of pad spacing violating net class rules? I have wondered whether net class rules are too simple; so that if you have 500V relative to ground but only 1V between two nets, you should not need 500V spacing between those two nets.
On the subject of true Kelvin resistors versus putting 4 or 6 terminals down for a 2 terminal resistor, I think it is a question of mfg control of the resistor construction versus that of your soldering. Getting down to micro ohms and how thick is the layer of fused solder between the pads and the resistor? Are you measuring IR drop in the solder between the pad and the resistor? etc. In theory I would like to think that the manufactured Kelvin resistor is better but I have no data to prove that is the case. I guess that some well controlled soldering with a 2 terminal resistor might be better than a poorly manufactured 4W resistor.
I was reading some of the forum posts about net tie’s a few days ago and created what I think is equivalent to a net tie on an inner layer. To do that though I had to rely on the info of another post that described manually changing the layer in the component file. So, I initially created the pads and graphics on the top or bottom copper layer. Then I opened the kicad_mod file using an editor and changed the layer for those elements that I wanted on an inner layer. When I open the component again in the footprint editor, they appear correctly on the inner layer. I have not attempted multiple inner layers but it appears to work for at least one. DRC runs fine on the component after setting up some custom rules.
its not net class rules being violated, its traces being added to the footprint that is causing some issue somewhere. Its simple enough to work around for now as you can place the net-ties within the footprint’s courtyard (one of the hacky things )
That is cheating! 
I think my net tie has two pads and I am not sure if I could have created two pads on an inner layer.
OK thanks. I am working on a new (home project design) and I am not nearly ready to run DRC. I think that my previous use of it connected to a belly pad…but apparently not to a copper zone which was the condition I was asking about in my original post. I think a net tie could be used to help implement Kelvin voltage sensing; I think the net tie could be (this is not quite ideal) connected between two trace ends rather than directly connecting to a resistor pad.
On the subject of Kelvin voltage sensing I think there is likely to be some variability in results when starting with a 2 terminal resistor. There ought to be less chance for results to differ from manufacturer’s specifications if you start with a 4W Kelvin type resistor.
You are right that a 4wire will provide a more consistent measurement point as the tap point isnt via solder
However, when I was working on this I had other constraints
- availability
- common formfactor - at least 5 manf usebthe type I settled on.
Now this will start to be a problem when I drop below 500uR as the % difference due to solder is higher. That said my next design I am considering silver sintering instead to mitigate the variability in the additional ohmic connection
I think you are correct. I have not made a concerted search effort but there seems to be a lack of standardization in footprints for 4W Kelvin current sense resistors; particularly SMT types.
Years ago I made a few current shunt boards which used 4W current sense resistors. I designed the board to accommodate 2 completely different leaded resistors.