its not net class rules being violated, its traces being added to the footprint that is causing some issue somewhere. Its simple enough to work around for now as you can place the net-ties within the footprint’s courtyard (one of the hacky things )
That is cheating! 
I think my net tie has two pads and I am not sure if I could have created two pads on an inner layer.
OK thanks. I am working on a new (home project design) and I am not nearly ready to run DRC. I think that my previous use of it connected to a belly pad…but apparently not to a copper zone which was the condition I was asking about in my original post. I think a net tie could be used to help implement Kelvin voltage sensing; I think the net tie could be (this is not quite ideal) connected between two trace ends rather than directly connecting to a resistor pad.
On the subject of Kelvin voltage sensing I think there is likely to be some variability in results when starting with a 2 terminal resistor. There ought to be less chance for results to differ from manufacturer’s specifications if you start with a 4W Kelvin type resistor.
You are right that a 4wire will provide a more consistent measurement point as the tap point isnt via solder
However, when I was working on this I had other constraints
- availability
- common formfactor - at least 5 manf usebthe type I settled on.
Now this will start to be a problem when I drop below 500uR as the % difference due to solder is higher. That said my next design I am considering silver sintering instead to mitigate the variability in the additional ohmic connection
I think you are correct. I have not made a concerted search effort but there seems to be a lack of standardization in footprints for 4W Kelvin current sense resistors; particularly SMT types.
Years ago I made a few current shunt boards which used 4W current sense resistors. I designed the board to accommodate 2 completely different leaded resistors.
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