Copper Zone vs Netclass Clearance question

[gschelotto]

Setting the Clearance Board Setup (for example) to 0.2 mm and the Copper Zone Clearance to 0.1 mm leads to a global layout Clearance of 0.2 mm.

I think that a setting of a Copper Zone Clearance < Netclass Clearance should be avoided.
Am I wrong?

[Piotr]

@gschelotto

I think that a setting of a Copper Zone Clearance < Netclass Clearance should be avoided.

I think you need not to avoid it. It will be ignored as KiCad uses the biggest clearance regarding a given situation.

[paulvdh]

What do you mean with:

@gschelotto

Clearance Board Setup

There are several different clearances in the board setup, and on a world wide forum confusions about this are easily made.

But in general, I think the settings in the board setup are supposed to be the minimum that your PCB manufacturer can reliably make (which is often assumed t be 20% to 30% coarser than what they state on their websites). Other clearances are used for other purposes. You may want to increase a clearance to reduce capacitive coupling, or apply bigger clearances for higher voltages.

@gschelotto

I think that a setting of a Copper Zone Clearance < Netclass Clearance should be avoided.
Am I wrong?

A simple rule like that does not make much sense. There are different clearances for different purposes and the clearance should fit the goal. And as Piotr wrote. KiCad compares the clearances with each other and takes the biggest specified clearance between copper items on the actual PCB.

[gschelotto]

Thanks for clarify this. Now I agree with the current behavior.