As you can see in the center of the image, there is a bridge between the resistor and the MOSFET, going through the pad of the resistor. In KiCad 6 this doesn’t happen (pic in the reply below, new users can only upload one media item ), which means that the MOSFET ends up with a much worse connection to the copper zone.
Both pics are with the same zone settings. Is there some way to force the zones to bridge between pads?
Both pics are with the same zone settings. Is there some way to force the zones to bridge between pads?
copper zone properties dialog → pad connection → change to “Solid”. (change belongs to whole zone)
If you want to connect only the 2 described pads with a solid connection:
doubleclick the resistor/mosfet-Pad–>Pad Propertis dialog–>Clearance Overrides–>Pad connection to copper zone–>solid
or place a second “+BATT”-zone (with higher priority and thermal-setting==solid) between these 2 pads
Yes, I can use solid to force the connection, or even just run a trace between the pads, but I was looking for a solution that works on all the zones without having to manually change each one
You could also try the setting in “board seup–>Design rules–>Constraints–>zone fill strategy”. There is checkbox to switch between performance/legacy behaviour. Maybe this shows a difference.
To me it looks like you are using very wide thermal spokes, and those spokes are about the same width as the pad for the resistor.
These obviously is a high-current tracks, and using thermal spokes here is not a good idea.
I was thinking if this should be treated as a possible bug, but it looks more like mis-use of KiCad.
You can change zone itself to use a solid connection, and then export the zone properties to the zones for the other fets. Changing this is less work then starting this post and making the screenshots.
If your problem is with the width of my thermal spokes, I can definitely change them, but the problem persists, so I don’t see your point. If the connection didn’t carry as much current and the spokes were thinner, the issue would still be there.
As for if it should be treated as a bug, there is a clear difference between KiCad 5 and 6, and from what I can see the one that is working correctly is pretty obvious, so blaming the user doesn’t seem like the right strategy here.
Furthermore, it’s pretty obvious that there is a difference in fill behaviour, if you import a board designed in KiCad 5 to KiCad6 and re-fill all the zones, without changing settings, the clearances will be significantly reduced, and routes will be disconnected because of the weird “no zone through pads” behaviour.
Please don’t forget that I’m just guessing what may be the cause from some screenshots and a short description, while you have probably been working on this PCB in KiCad itself for a day or more.
KiCad has to change in order to be able to improve it, and small things like this may be the result of that.
And such changes are often a reason for not changing a program version halfway a project, especially if you do it for a living instead of for hobby.
), which means that the MOSFET ends up with a much worse connection to the copper zone.
