Trying to understand copper pours a little better. I have had the same issue from v5 to now v8.0.7 I have known about a 0.0005mm discrepancy but no idea where it comes from
If I want to create a GCPWG line, with a trace width of 0.51mm and a gap to the ground of 0.295mm I have do the following.
Create a footprint with three pads. Ground, Signal, Ground in the library. Measured to have a gap of 0.295mm between ground and signal.
If I lay this on PCB, draw a trace between them of 0.51mm. The default clearance is 0.295mm. I then do a ground copper pour to go around the trace (clearance of pour is 0.15mm). The copper pour is always 0.0005mm too large. I have to change the clearance of the line to 0.2945mm to get the pour and the pads to have a continuous straight line. Granted this 0.0005mm offset isn’t going to be a major issue during manufacturing but would love to know how it is generated.
How do you know about such a small discrepancy? My understanding is that the native resolution of KiCad is 1 micron, and I think you are describing 0.5 micron.
Why do you care about such a tight tolerance? I do not think that any PCB fabricator is that precise. I think that even 1 mil = .0254 mm = 25.4 microns is pushing the state of the art for etching PCBs. When I started in electronics around 1974, resolution in ICs was maybe 2-3 microns. You are trying to resolve finer than that for some reason (???)
As a new poster I guess maybe you cannot post images, but if you can do so it might help.
Grounded co-planar wave guide apparently. Never heard of it
KiCad does have a 1nm resolution, so 500nm is much bigger and this should not happen. Maybe you’ve set up some other clearance that dominates in your postition. To check this you can:
Select the zone
Press [Shift]
Click on a pad or a track segment to select it too (so 2 items are selected).
PCB Editor / Inspect / Clearance Resolution
This tells you which clearance is active between those two items.
I did some measurements, and the auto-generated clearance between a zone and some other item does indeed appear to be 500nm bigger then you’d expect it to be.
A long time ago (several years) there was a bug for rotated footprints. If the pad width + clearance was the same as the pad pitch, then this worked for footprints at a multiple of 90 degrees, but not for rotated footprints. From what I remember, a tolerance of 1nm was added to the tolerance for DRC clearance violations back then. But there may be other reasons.
Hi BobZ
Yes I am unable to upload at present. From a manufacturing point of view it isn’t necessary but when reviewing gerbers if you zoom in you can see the little jump and just wanted to determine why it requires me to have the offset to make things smooth.
PaulVDH,
I tried the clearance resolution and it comes up with 0.295mm… This is a completely fresh PCB project with one trace, one pour and two footprints with the ground signal ground configuration.
Was just curious if anyone had come across it before or if it is a maths feature.
It probably have something in common with reported by me 0.001mm error (track width so 0.0005 at each side):
I didn’t reported this 0.001mm because of 0.001mm but because KiCad filling zone with some rules and then complaining that rules are broken.
This issue was closed 2 weeks ago so in 8.0.7 you don’t have it (but may be only complaining was canceled). I suppose that from some calculations reasons they need to left some extra space when filling. Have in mind that there are not only straight lines in the process but also for example rounded pads and rounded filling complicating (a little ) exact calculation of clearance between objects.
ekoeck:
Tried your suggestion. Same outcome of a small offset
Tried with trace default clearance of 0.15mm and zone clearance of 0.295. Same outcome with small offset
Piotr: Interesting. Might have to submit a bug report and see what happens
