I have a four-layer layout, built with KiCAD v5 (the original 5.0 release) — the layers stack is:
- Top copper (components and signals)
- Ground plane
- Vcc plane
- Bottom copper (signals)
I have many filled-zones on the top copper layer — some ground zones to connect the “power VDD” decoupling capacitors, and zones to provide extra-thick connections from the IC’s output pins to the output terminals (these are signals carrying 5A to 10A).
The layout passes DRC with “zero errors, zero warnings” (only the “Refill all zones before DRC” and the “Check courtyard missing in footprints” boxes are checked)
Now, I want a copper pour connected to GND on the top layer — my idea is: add a zone for GND net, with
Default pad connection set to
None, a 0.5mm clearance, and then edit some of the vias or pins connected to GND and set them to override the “Pad connection” (e.g., set it to
Solid) to make a connection to the zone and thus make it fill.
Well, it does not seem to work: the zone just fills on top of all the other zones. Now the DRC of course flags 50+ errors (Copper zone within copper zone).
The priority of the just-created zone was 0; if I increase that priority to a value above any other priorities in the other zones, then the other zones do not fill, and I get a bunch of ratsnest lines showing missing connections.
In case it matters — the filled zone I’m creating is a square, essentially the same as the board’s edges.
Is this a sign of something wrong with the layout? Or is this “normal”/“expected” behaviour? (I would be greatly surprised if that was the case)
I guess I could carefully draw the copper pour in selected areas; and for that matter, I’m sure I can live without the copper pour — still, I’m puzzled and curious (and would prefer to have the copper pour connected to GND)