Hi there,
I have a hard time understanding how copper pours work. I’am creating a PCB in where I want to follow the layout guidelines of the ICs manufacturer. So I created a filled zone area for GND touching all the pads that should be part of the copper pour and filled it by pressing “B”. Instead of having a completely filled area it would respect the clearance settings of the involved pads. How could I achieve a completely filled area?
Screenshot attached.
Thanks Jens!
There is not enough space for it to create the thermals.
That’s often a starting point for understanding situations like this but it doesn’t point directly to a solution.
In my mind your question is just a little bit ambiguous - are you trying to get the pads completely incorporated into the filled zone, without any thermal relief? (There are times when this is definitely the best approach, though assemblers may curse you for doing it.) I think that is best accomplished with settings in each pad’s definition.
There are several inter-related parameters affecting a filled zone. These include net default trace widths, clearance to other pads and traces, width of the thermal spokes, size of the “antipad” areas, and minimum line width within the filled zone. Some of these factors may be defined in more than one place - board global settings, in the filled zone’s definition, at the component footprint, or for each individual pad. (And I’m not sure what the order of precedence is.) I know it sounds quite un-scientific, but play around with some of the values and see what happens when you refill the zones. Be bold with your experiments, changing parameters to half or double the default values, until you get a feel for how these things interact in your specific situation.
Dale
I don’t understand why the bigger housings (green) to the bottom left and right of that 10 pin IC are arranged like they are.
Wouldn’t it make more sense to rotate them with their GND pads inwards (reducing the copper pour area and making it more simple) and sort out that little fella (blue) with the vias to the left of the IC?
All else - @dchisholm has covered it already - nothing to add there.
Hi Dale,
thanks for your detailed guide on how I could tackle this type of problem! I had already checked the pad copper zones setting and the numbers were set to “0”. however the default pad connection ist set to “from parent footprint”. When this is changed to “solid” I don’t have the thermal reliefs anymore.
@Joan_Sparky:
I wanted to try to stay as close to the vendors design as possible (even if at this stage it’s not very close due to me fiddling around) I’ve attached an eagle screenshot of the design that I downloaded from the TI homepage (the ic is a bq24095 lipo charger).
So what they did is introducing 2 GND planes north and south of the IC that meet on the bq’s thermal pad and west and east copper planes for in and out positive power connection.
I thought it’s wise to stick to that “design” idea as much as possible.
Ok, so I converted the eagle reference design board to kicad which is a bit better to analyse then my current board. Although they (TI) gave everything a bit more space I see the same type of issue. The north / south GND layer which should meet beneath the IC is disconnected due to the thermal reliefs. I’ll start to convert some of the pads to solids unless somebody can point me to a better solution.
Thanks,
Jensbq24095 reference design.kicad_pcb (95.3 KB)
Looks like the fill zone, the IC’s thermal pad, and the set of stitching vias are associated with different electrical nets. Check their respective properties and make sure they are all associated with “GND” (or “COM” or “RET” or “PGND” or whatever you call it in this design).
Dale
I think I got it right after a lot of tinkering. The main steps to avoid thermal reliefs when not desirable because you want a copper pour to act as a heat sink or thermal reliefs would disconnect your copper pour from pads when using very small structures:
BTW, I kept thermal reliefs where I beliefe they do not harm.
Thanks again for all the support in this topic!
Jens
That looks like very good work! You should be proud of yourself!
I am also confident that the steps you listed will be helpful to other users in the future. I wonder if Texas Instruments would consider publishing a set of KiCAD design files for this project on their web site. Of course, that would help them sell their products but it would also promote KiCAD.
Will this board be hand soldered, even if it’s only for a few prototypes? If so, please consider enlarging the size of the thermal pad under the IC so it will stick out a small distance beyond the edge of the IC package. This small area, without solder mask, makes it much easier for a soldering iron to make an effective solder joint.
Congratulations!
Dale
Wow, what a nice feedback. Thanks a lot, Dale! This board will be soldered with a home brew vapor phase solder station since I had little luck soldering QFN packages by hand.
I’ll increase the size of the thermal pad as per your advise, who knows when the vapor phase solder unit will be ready.
Concerning TI and KiCad. I’m happy to help them 
But I doubt they are interested. Even nordic guys which are known to be very community / maker friendly didn’t manage to export their nrf51 reference designs into something else then altium designer.
