Copper pour/fill and distance to the PCB edge

Hi, I’m trying to prepare my PCB design for OSH Park. One of their rules is that the distance from traces to the PCB edge should be 15mil.
I’m in a bit of a pickle. In design as can be seen in image, I’ve drawn board layout (with arcs at the corners) and used this board dimension to create zones (4 layers). Currently, in design rules of the PCBnew, clearance is set to 6mil and to increase that to 15mil doesn’t have any sense to me. I can keep tracks out of that border area, but what about copper fill (I’m scared if milling machine could do something bad)? As far as I can understand it, milling head will enter the board edge line to the middle of it (OSHPark FAQ). Only solution that I can think of is to resize copper zone, i.e. shrink it by 10mil (+6mil clearance).

P.S. Does anyone know, if I order PCB in February, how much would/does Chinese New Year influence delivery date? Does it make sense to pay for express shipping then?

As to answer your question on Chinese New Year. OSH park is completely USA. All the boards are made in the USA. So you won’t have any problems with Chinese New Year :wink:

As for the copper pour. Most of the time the router bits won’t have any problem with milling through copper. The only thing is that they will wear out faster, and that is a thing the fab does not like of course. My guess is that is why they check for this kind of things.
What you could do is just upload your design to OSHpark and they will check it. If something bad comes out of it, they will tell you, if not, the fab will just make the boards for you.

What might be a problem is that they will cut off some of your copper pour and that, therefore you won’t have enough copper there to make the path. So if it is essential that the copper stays there, you might check if losing some copper near the edges will break your design.

One issue with milling through copper on boards with many layers is that copper is soft. You may end up with a bit of copper getting smeared across exposed copper, shorting things out. This may not be an issue yet with a 4 layer board (assuming 1.6mm), but cannot be ruled out completely (dull router bits exacerbate this).

I think this is an unnecessary complication.

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Is there a solution for that now ?
I have round corners too and I want to have 8 mil clearance in the filling area to other signals,
but to the edge of the PCB I want 20 mils clearance.
What is the best technic to reach it. Maybe drawing a keepout zone with round corners ? Or is there a better way.

Hi ado,
in my example (using the old stable BZR4022), I’ve chosen 6 mil for the clearance inside the zone(s) Settings/Params, and that brought me to the desired clearance (that maximized the amount of ground plane) for my layout.

To affect the border clearance (as per the manufacturing requirement), on my own account I took a chance and drew inside the Edge.cuts layer a layout (lines) exactly on the border of my zones. Since I had selected 6 mil clearance for the zone(s), and traced lines 18 mil thick, which when divided (1/2 inside a zone, other 1/2 outside) gave me 9+5 = 14 mil clearance from the zone border to the coper!

Design was (superbly) produced by OSHPark without any problems (as far as I know), and I got what I wanted.

P.S. I haven’t responded here earlier with the response, because I think it’s a bit dodgy approach.

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The idea to draw an extra line to expand the clearence between the filled zones to the edge of the pcb is a useable solution, I guess. For the Top and Bottom Layer I had no worrys about place the filled Zones nearly to the edge of the PCB. In worse case, I had to make some rework with a file.
In my case I have a 4 layer board with big inner lying big plate areas.
For security, I just redraw the areas exactly 0.5mm of the edge cut line and in the arcs I just make 45° lines.
It’s just a proof of concept board. So what the hell.

I hope sometimes there’s a seperate parameter for the edge cut / filled zone clearance.
Or maybe I overlook the option for that.

You might be able to use this bug to your advantage:
[Bug 1516244] Re: filled zone clearance influenced by edge.cuts line width

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Thanks for this solution und it works proper.
I tried this exacly like this some days ago but it doesn’t work.
I assume I forgot to recalculate the zones again.

In my opinion it’ s not a bug. It’s the way of doing the PCB-Edge/filled Zone clearance.
I’m not a fan of the way but for me it’s important there’s a methode of doing this.
In my case my PCB-cut-edge is now 1mm thick. It looks not so nice, a layout perimeter line that thick.
I would prefer a user selectable line width for just optical reasons, not for technical.
And the clearance of Edge-Cut/Filled-Areas were a dedicated parameter in the options menu.
But for now I have a solution. Thanks a lot.

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So thickening the cut-line will increase the clearance zone from the edge, but what if I want to make it thinner than the clearance on the board? ie I want the copper go right out to the edge of the board. I could increase the size of my board by the clearance width but that seems like a clunky work-around.

Should be a separate property for fills.
Pcb edge spacing.

I wish.

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I second this and ran in to a similar problem. Accomplished it by using zone fill keepouts. :expressionless:

It lives! Seriously though, for reference, KiCad 5 seems to have a copper pour property called “Clearance”. Nowadays I think this is what you want.

Not really, because it affects also copper/copper clearance.

KiCad 5 has a workaround: copper zones avoid the edge of the Edge.Cuts lines, i.e. if you make them thicker the clearance from the middle of the line is larger.

KiCad 6 will have a dedicated edge clearance (can be tested in the nightly builds).

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