Copper pour does not connected to pad which is on the same net class

on the top side, there is a C9, gnd pin is the upper pin, which is connected to gnd by a via, the lower one is supposed to connect to 3v3 copper pour, but it does not, i wonder why.

sorry, wrong image file

It would really help if you at least circle the affected component such that we can find it.

In most cases where people have such a problem the culprit is the clearance and min with setting of the zone. In your case the settings for the thermal relieve might also be to blame.

To make a better assessment i would need to find the component so please give us a hint where to find it.

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Have a look at your usb connector.
Is it USB_Micro-B_Molex-105017-0001?
You should update your footprint. (One of the pads has the wrong zone connect settings. That’s why only three of its shield pins are connected to your green zone.)

You might also need to get this connector nearer to the pcb edge.
(The connector should protrude the pcb edge.)
From the datasheet

It is, i have to cut the edge flat, but it is not easy to do that in kicad.

I hope this does not prevent the plug fully pluged in,

You can create the outline in any cad program export it to dxf and use kicads dxf importer to get it into the pcb file.

You might want to increase the segments for the zones…you have 16 now for the full arc… 32 is max, and will look a little bit better.
For more segments (I’d want at least 128 per full circle) you have to use a custom zone outline, that you have to add to the .kicad_pcb file manually. A script for creating those coordinates from me is on github.

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I found C9: And you definetly have very large clearance settings. (although it looks like it might still be connected to the right.) Do you expect high voltages or is the current clearance an accident?

Every zones has their own clearance settings. (In the zone properties dialog. Press e while on top of the zone outline to access it.)
They do not follow the settings you make in the design rules.
The default zone clearance is very high. (0.5mm or so) You can drastically reduce this setting.
You can also play a bit with the thermal relieve settings.

Yeah,that is it,

I used to do dxf stuff in poerpcb, but now i am on linux, and i did not install mcad yet.

A lot better really, it is enough for me for now.

Freecad and librecad work quite well together with kicad. (libre cad shares the same geometrical kernel as the dxf engine of kicad. At least if i remember correctly.)

I changed it from 0.508 to 0.40, now it is all right.

another problem though,

Goog to know, i will try that out later.

i chose 105017 for footprint from kicad library, 3d shape from joan_thr_sparky github repo, i believe,

and i knew there are all kinds of micro b socket, that will not be a problem?

I thought it is bcz of offset ?

Not sure what your question is.

My observations:
Update the usb footprint. it had a problem until yesterday. (I merged the fix a few hours ago. See the github link i gave in one of my upper posts.) That is the reason why one of it’s pads is not connected to your GND plane.

The cross through your holes stems from the thermal relieve stuff. I’m not sure why this is shown this way in the 3d viewer. Maybe there is an option to drill through it. (Your finished pcb will not have these crosses inside the drill.)

I think you can still reduce the clearance settings of the zones. (But i don’t know your isolation requirements. And i don’t know the capabilities of the fab you will use to produce the board.)
In most cases there is not really a reason to have a larger clearance between zones than between traces.

I will download the footprint later, there are a lot of emc stuff i ignored, this is a led dimmer. 4 pwm pass though the led driver, will certainly cause problems. There is temp sensor r13 connected to adc1_in,etc

The cross in the hole is result of gnd copper pour, i will draw keepout to prevent them showing up. It does not matter i think.

the default setting of zone clearance setting is 0.508, the clearance between track is 0.25.

Look up what your fab is capable of doing. I bet you can reduce both clearances.

(nightly version, not stable)

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It is 4.0.7, compiled by gcc-4.2.4, can not get github nightly built, lots of compile error. (426.5 KB)

I changed the clearance to 0.254, will send to fab later.