Copper pour creating odd bubbles around SMD pad corners [pic]

Layout
1

Hey all,

I’m trying to make a coplanar waveguide layout in KiCad, and I was able to get the clearance between my traces and the copper plane 5mil the way I wanted it. But, whenever filling in the pour zone, weird things happen around my SMD pads (0402 capacitor landings). An image of the effect can be seen here http://imgur.com/yYvC3kg. My question is - is there something wrong with my 0402 pad instance? Is there a way to maintain 5mil clearance throughout?

Thanks for reading

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It looks like Kicad is trying to put thermal reliefs around your 0402 SMD pads, as if they were supposed to be connected to the copper plane. I see the 0402 pads aren’t actually connected to the plane, so maybe there’s something inside your pads that’s trying to be connected to the plane but the pads are keeping that from happening.

If you just drop a 0402 footprint with no net connections into the plane, what happens to the plane around its pads?

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This is a bit of a weird one, I’m not sure what’s going on, it looks like the fill has got confused because there are no net names, did you do a schematic?

As a general tip though, if you’re doing RF stuff you usually want to set “Pad connection” to solid in the copper zone properties, this may well fix it in this case. It can be a tricky one for manufacturing because you have parts directly connected to the ground plane which can cause tomb-stoning but if you use thermal relief you add a small capacitance and inductance to every ground point which can cause all kinds of problems for RF.

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Hey guys,

Thanks for the replies! Nathan - I double clicked on the copper zone properties, and changed “pad connection” to “solid”. Gave me this result http://imgur.com/A00sHgg looks like that fixed it :slight_smile:

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Glad it worked.

I think the fundamental cause is that the lack of a netlist is getting the fill algorithm “confused”. At a high level all the pads and the fill have the same net “no net”, so it goes to join them all up with thermal reliefs then at the low-level check it finds that the “no net” net is special and doesn’t actually join them.

If you draw a really simple schematic for this and export the netlist this kind of thing shouldn’t happen regardless of your pad connection settings.

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Ya, it seems like all the pros make a schematic first. I guess a lot of my problems would go away if I linked a netlist to my pcb layout, but I’ve never done that kind of thing before. But if it will save me headaches in the future, seems like it must be worth the time