If I were to make an inner layer ground and have no fill on the top and bottom that would require a significant amount of vias connecting the components on the top & bottom layer (considering gnd is the most popular track). Doesn’t the increased use of vias come with it’s own negatives (impedance)?
I have four power lines, all DC. There’s no RF/filter circuitry on the board and EMI is not a concern. There are a few PWM circuits that can cause noise but they’re all to the side of the board.
L1: red: mostly component connections, moderate GND usage.
L2: pink (mostly power traces).
L3: mostly MCU tracks where tracks on L4 couldn’t work)
L4: green: mostly component connections and significant GND
How much power is involved,and what decoupling do you have there ?
Usually with PWM, you try to keep lowest Power supply loop impedances, for noise/radiation.
What is the main IC ?
If you have stacked fragmented GND planes it’s common to use stitching vias, to try to make them ‘average more solid’. ie around the IC package, keep under that clear so vias can connect one side to the other on an inner layer.
That also means you try to spread traces to allow all GND vias to connect - on your yellow layer under the main IC, it’s quite good (connects left-right ok), but below that are 2 isolated GND vias, that some simple trace moves can allow to connect better.
Also to the left, a trace can move to give broader GND flows, to other GND areas.
The main purpose of plane layers (ground or power, doesn’t matter) is to minimize current loop area (and thereby radiated emissions and susceptibility) by controlling RF ground return paths. Planes do not add appreciable distributed capacitance unless you use a special PCB process with very small layer spacings and even then the amount of capacitance is small and only significant at high frequencies. Any discontinuities in the plane layers will defeat the purpose of loop area minimization for any tracks in adjacent layers that cross a discontinuity. Copper pours in signal layers (as you show) are generally pretty useless but can reduce in-plane crosstalk between adjacent traces if properly grounded. If not properly ground they can make emissions worse. Vias do have impedance (everything does) but at low frequencies you shouldn’t have to worry about that. The larger the via the lower the impedance, and of course you can use multiple small ones to similar ends.
Using a continuous ground or power plane adjacent to a signal plane is pretty much always good practice and has no downside if your board’s floorplan is well-partitioned. Chopping a plane into sections (as for multiple power supplies) needs a lot of thought in high-frequency design, but if you don’t have anything over a few 10s of kHz then don’t worry about it.
If you have an environmental friendly mind-set . . .
Current processes for manufacturing circuit boards start with a layer of foil covering the entire board, on both inner and outer layers. The copper is then chemically etched away except where pads and traces are required. Adding fill zones reduces the amount of copper that must be removed, which in turn reduces the amount of chemicals that must be used and reduces the amount of chemical waste material that must be treated and disposed.
This might be relevant if you are etching your own boards at home but the topic is about inner layers so that’s not likely the case here. If the fab making your boards is not environmentally friendly then nothing you do on your board is going to make a difference anyway, and if they are then again, nothing you can do on your board is going to make a difference as they already recover both the copper and the chemicals. So this should not be factor in design considerations.
Lots of good points here, davidsrsb that’s true for prototyping, good point.
I was asked earlier, the MCU is a PIC32, 12-24MHz but the crystal is on the same layer and close by. The fat voltage lines on the pink inner avoid this area (on purpose). The PWM’s are mainly for driving LED’s so aren’t high frequency. There’s a 2.2MHz boost converter but the few components are above each other on the outer layers and at the edge of the board. A bluetooth module sits away from everything else. There’s a USB port and the clock is 48MHz. Hopefully these lines won’t suffer any EMI but that is one area where I could have ran the signals on the exterior plane.
I do not see a ground plane on any of the 4 layers ???
All zones are cut into little pieces by long traces.
I also do not see many “via stitches” as an attempt to connect the different parts of ground planes.
The planes seem to have been added as an afterthought, and not designed in.
If the black cutout on Green and Red is for the bluetooth antenna, then the cutout should be on all layers.
That is correct Paul. Originally I was using GND on the back, a relic of my two layer thinking. The dual sided SMD soon put an end to that. I had filled the inner layers but left them floating.
It did look like some ad-hoc designed pcb that grew into this
Is this a hobby product or commercial? Does it have to pass EMI tests?
For a single chip uC design the layout is not too critical.
PCB layout becomes difficult if you have multi chip designs with several hundred MHz clock frequency.
(A long time ago) I read some article about decoupling HF digital design.
They placed the decoupling caps as near as possible to the Chips’s as possible, then a short trace and a via to the GND plane. The inductance of that short trace & via kept most of the noise that the IC’s generated out of the GND plane itself
If you make sure that the decoupling is done properly then have a close look at stitching the GND plane parts together. Sometimes you can pretty easily move a few traces from your GND plane to another layer to make it more continous.
If you have signals that switch a lot (PWM, SPI) then try to put a GND plane under them.
Ideally the return current of those signals would be able to follow the same path through the GND plane.
I can not see what all those (parts of) planes are connected to.
As noted before: Close capacitive coupling between GND plane and VCC plane is good for decoupling.
Other nets should (almost ?) never have copper fill.
Copper fill to unconnected nets is not good.
Based upon stackup, its best to keep each step of the construction of the board similar in copper density per side,
Its not seen as much, but a solid plane on 1 side, and a few traces on the other of a long board will lead to it curving,
So if your having a 4 layer board made out of 2x 2 layer pcbs, then your inner and outer pairs should be similar, and if its a 2 layer core, and 2 single layers stacked on, them the inner layers should be even, and the outer ones somewhat close, but far less important in this stackup.
So lots of ideas. I’ve learned that > 4 layers isn’t necessarily for track placing but for sandwiching GND planes between signal tracks.
As I’m using 4 layer and dual sided SMD, quite condensed, there’s no scope for making layer 2 or 3 fully GND. Even if I did it would still make one of the outer layers susceptible to EMI. However, in my case I believe EMI will be limited plus the board doesn’t need certifying in that regard.
I’m now on prototype #4 after ballsing the PIC32 footprint. I’ll incorporate some of the suggestions;
No unconnected islands on any layers
More GND vias
It appears most approve of filling all layers with GND copper even if entwined with power tracks (as per the middle layer). If not, speak now.
No they don’t.
Consensus is about a single large GND plane without interruptions.
Return path of high frequency transients in signals should be able to follow the same path in the GND layer as they do in the signal layer to minimise loop area.
But in an already finished PCB layout some random extra via stitching willl probably improve the design.
The snag with islands of copper on the outside that are connected to an inner plane in just one or two places is that you have just made a patch antenna and when driven somewhere away from the via you get worse radiation than simply using a track to the via.
People love saying you must have an unbroken ground plane. But rarely look into why its a rule of thumb.
If your signal transitions from high to low in under 10us, the return path current is going to alteast in part follow the path of least impedance instead of path of least resistance
Because of this it becomes more important to provide a way for that current to follow your signal trace as closely as reasonable.
The goal is to keep the coupling between signal and return high, when it has to detour around a cut, you create a unintentional loop antenna, the bigger the detour, the more likely it will cause you greif.
Now the easiest workaround for these cases is to provide a way for that current to stay near the signal over cuts, e.g. on a 2 layer board, when 2 traces cross, throw some ground plane vias so the signal current can hop over to the same layer as the signal, then hop back down on the other side.
This may create a small loop, but in almost every case its far better than the alternative. This will also create a small mismatch in length, however by the time 2 via lengths of mismatch matter, your already facing harder challenges.
This also applies to signals changing layers, if the edge rate is high, provide the ground current a path,
Ok guys, since I had to change the pic I’ve spent a few days improving the design by removing most tracks on the inner (yellow) layer. The outer GND planes on top/bottom have been removed.
It has necessitated many more VIA’s. Still a bit of work to do but getting there…
