Copper and mask in different layers

This post is somehow related to How do I create a soldermask on a pad different to the pad itself?

I am using a python script to generate footprints, and was looking into generating pad and masks separately.

However, I am having DRC connection issues. This is my kicad_mod:

  (pad "" thru_hole circle (at 0 0) (size 1.2192 1.2192) (drill 0.4) (layers F.Mask))
  (pad "" thru_hole circle (at 0 0) (size 1.2192 1.2192) (drill 0.4) (layers B.Mask))
  (pad 1 thru_hole circle (at 0 0) (size 1.016 1.016) (drill 0.4) (layers F.Cu))
  (pad 1 thru_hole circle (at 0 0) (size 1.016 1.016) (drill 0.4) (layers B.Cu))

Any idea what I am doing wrong? I have tried changing SMD to thru_hole, but I still get a DRC error that B.Cu and F.Cu are not connected.

Note: of course, the best would be to define a single Pad on *.Cu and *.Mask with solder clearance, but I need to this separately for some corner cases where mask shape is not same as copper shape.

Thanks in advance.

I’m sorry, but my crystal ball is gone for maintenance and it’s taking longer then expected, so in the mean time we’ll have to do this the old fashioned way.

It may help if you show us the complete DRC error messages, or even better, make a dummy project with your Footprint and upload the whole project here.

It makes no sense to define a mask only pad as through hole. Use smd pads for that. The important part is that the pads that define only mask can not have a pad number.

As an example look at any footprint in the official lib that has a soldermask defined center pad (you can identify them by having the keyword “mask” followed by the mask cutout size in the footprint name)

It also makes no sense to define a thorough hole pad as touching only one single copper layer. After all the drill goes through all layers and you want plating on all layers. So if the copper size should be different for some layers then make a through hole pad with the smallest size in the pad stack and place larger SMD pads with the same pad number on the layers that need a larger pad.
See any footprint with “ThermalVias” in its name.

Thanks for your quick replies. Please find attached here the a simple PCB board where I experience this. The “_Fused” version has no DRC errors, whereas the other one has all the elements disconnected because of the separation of subpads. (139.1 KB)

For more complicated boards, the pad has a different size in inner layers than in F.Cu and B.Cu, that is the whole motivation. But the through hole size is always the same in all layers.
So your suggestion Rene would be to have this type of combination?

  • pad “” smd circle *.Mask
  • pad 1 smd circle F.Cu someSize
  • pad 1 smd circle In1.Cu someOtherSize
  • pad 1 smd circle B.Cu someOtherSize
  • pad 1 thru_hole *.Cu *.Mask drill XYZ

Ok, I think that this would solve it, but does not:

  (pad ~ smd circle (at 0 0) (size 1.016 1.016) (layers F.Cu)
    (zone_connect 2))
  (pad ~ smd circle (at 0 0) (size 1.016 1.016) (layers B.Cu)
    (zone_connect 2))
  (pad "" smd circle (at 0 0) (size 1.2192 1.2192) (layers F.Mask)
    (zone_connect 2))
  (pad "" smd circle (at 0 0) (size 1.2192 1.2192) (layers B.Mask)
    (zone_connect 2))
  (pad ~ thru_hole circle (at 0 0) (size 0.4 0.4) (drill 0.4) (layers *.Cu *.Mask)
    (zone_connect 2)) (73.6 KB)
(this the version following the pad definition from above, that still shows unconnects.

placing smd pads on an innner layer is not really supported. Real padstacks are also sadly not yet in.

However in most cases if the inner layers are different from outside then they will be smaller than the outside pads. So make the tht pad of the size you want the inner layers and place larger pads for the outside where you need more space for solder.

If I look at this board it’s got at least 4 different “paper” layouts stacked on top of each other, and I’m not even sure where to start looking among the different pads.

I’m also more of a visual guy then Rene. (But I can read).
So I took a small Footprint which has ThermalVias:


On the PCB it looks like:

The important thing to notice in this screenshot is that the Thermal pad in the center is actually made from 8 individual pads. 6 THT pads and 2 SMD pads (for top and bottom). [Edit:] It’s actually more, because the 4 solder paste area’s are also made from individual pads.

In the 3D viewer it looks like:

and you can see different sizes for the solder mask and solder paste cutouts.

Here another view from the 3D viewer, with these layers turned off:

  • [ ] Board Body
  • [ ] Show Soldermask Layers
  • [ ] Show Silkscreen

I have also set the board to 6 copper layers.
Because I turned the outside graphics of the PCB off, you can see through the board. In the screenshot below, you can clearly see that the rings on the inside layers (from the THT holes) are much smaller then the SMD pads on the outside.

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Thanks for your help. I have followed your idea of checking in the 3D viewer how my via looks like.

So, at least visually, it is well formed in the footprint editor.

I guess the DRC issue is about the ‘Nets’ not being well defined in the PCB. Which of the subpads should have or not Nets connected? All the copper ones (SM and through), but not the mask ones, right?

alright, I have solved the DRC issues by defining the net in all sub-pads, including mask ones.
Is there a rule for this? All have to be defined? or just copeer ones need the netcode? (Note, I am setting the PCB netcodes from script, that is why I am asking)

Thanks for your help!

In KiCad all pads with the same pad number have to be connected together to pass the DRC. KiCad’s pad “number” is an alfa numeric string, and can be just letters such as “pad”.

My guess (and it’s just a guess) is that KiCad only checks copper layers for DRC checks.

At least in the past kicad complained with a pad being left unconnected even if it had no copper. For that reason pads without copper have to be left without a pad number.

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