I also started with KiCad V3, although back then KiCad did not have real version numbers, but BAZAAR hashes were used as KiCad’s version numbers.
And I agree with the others. Your S100 boards may be simple, but KiCad has made a huge progress in the last 10+ years. On the KiCad website, the oldest release notes are for KiCad V4.0.0 released on 2015-11-29.
Back then KiCad projects were not independent. They relied on KiCad’s libraries being available. I just did a download of: http://www.s100computers.com/My%20System%20Pages/Z80%20Board/S100%20Z80%20V2.01.zip The PCB has a name on it that has a suspicious resemblance to your handle on this forum 
The downloaded project includes the [Project]-cache.lib file and that is quite important. Without that file, KiCad can only open the project if the original libraries are available (And I do not have the KiCad V3 libraries installed anymore).
I was curious and did a conversion of that project, and I had no problem with the conversion at all. The initial conversion to KiCad V8 took a few minutes, Then I went a bit further and had a look at both ERC and DRC. That takes a lot more time, but most of the time was for getting a bit familiar with your project and writing it all down. There are a bunch of minor issues (such as overlapping silkscreen), which I all ignored, and there was one bigger issue (Solder Mask Expansion) which I “fixed” with a few mouse clicks.
Below a more detailed report.
The schematic starts with the line:
EESchema Schematic File Version 2 date 2/1/2014 1:05:13 PM
And the PCB:
PCBNEW-BOARD Version 2 date 16/12/2016 21:45:47
# Created by Pcbnew(2013-07-07 BZR 4022)-stable
And I could open the project in KiCad V8.0.9 without much problems.
- Double click on the
s100_Z80 V2.pro file opens KiCad’s project manager.
- Open the schematic from the project manager.
- KiCad complains the libraries are not available. Click [OK].
- Remap symbols dialog. Click on [Remap Symbols].
- Project Rescue Helper dialog. Click on [Rescue Symbols]
- Remap Symbols dialog** Click [Close].
- I’m now in the schematic editor. Click on [Save] button to save the converted project.
- Open the PCB editor. It just loads and converts the PCB.
- Click [Save] to save the converted PCB.
On first sight it all looks quite plausible. Only the 74ls00 gates have an arc pointing the wrong way:
Then, running ERC gives 315 violations. This is not surprising, as quite a lot of additions are made to both ERC and DRC and more errors are caught, but it also generates a lot of crud that you may not be interested in at all.
- Warning: Symbol XXX has been modified in library YYY . This is a common annoyance. I think this warning is mostly useful for people who use database driven libraries. I ignored them all (Right click in the ERC message window, and “Ignore All”), there are now 42 violations left.
- Warning: Both XXX and YYY are attached to the same items. This is about labels. It’s not even a real “warning” just an informal message that a bunch of nets have two different labels. In that case KiCad has to pick one of the net names. Right click, and Ignore all … There are now 9 violations left
- Warning: Symbol U41 has unplaced units (Unit C). It’s an unused gate that you forgot to place in the “spares” section
- Warning: Symbol U41 has input power pins in units [Unit C] that are not placed.
- Warning: Symbol U41 has input pins in units [Unit C] that are not placed. So I placed the symbols, added “No Connect” flags. 6 violations left.
- Warning: Unconnected “no connection” flag. There are two of these in the “spares” section. Most likely these are just some left overs, but it’s possible KiCad missed converting some symbol. I deleted the two flags. 4 Violations left.
- Error: Input pin not driven by any Output pins**. There are 3 of these for U22, and one of this for U40. All four of these are because of a fault in the U39 symbol. The output pins of this 74S08 gate are set to open collector, while this gate does have totem-pole outputs.
All 500+ ERC violations explained in less time than it took to write this post. Now the PCB. Running DRC give 630+ DRC violations and 253+ Schematic parity violations.
- Warning: Silkscreen clipped by board edge. Ignoring these, 627 Violations left.
- Warning: Silkscreen clipped by solder mask. Ignoring these, 428 Violations left.
- Warning: Silkscreen overlap. Ignoring these 229 Violations left.
- Error: Thermal relief connection to zone incomplete. The GND zone is a patchwork of islands on both the front and back layer. There are no stitching via’s at all, but all the pins of the IC’s in this project seem to be connected with tracks. I thought that KiCad suppressed the thermal relief errors if pads are also connected with tracks. I’m not sure what is going on here, but don’t want to dive deeper. Ignoring these and 199 Violations left.
- Error. Rear solder mask aperture bridges items with different nets. This is a real issue. The solder mask apertures are so big, that copper of other nets gets exposed. This can lead to soldering errors, and this should really be fixed I set: PCB Editor / File / Board Setup / Board Stackup / Solder Mask/Paste / Solder mask expansion** to 0.1mm. (It was 0.254mm) 0 Violations left. (This also fixed the solder mask aperture errors for the front layer).
And now for the Schematic Parity
- Warning Footprint **C1 Value (47_uF) doesn’t match symbol value (47 uF). There are a lot of these and similar. I was curious to the result of Update PCB from Schematic [F8] (In the old version you had to create a netlist, and then import that into the PCB. This is deprecated and combined into [F8] which does this all simpler and quicker).
After this update, there are 0 Schematic Parity messages left. But it did replace all the underscores in the values with spaces (Same as in the schematic), and it did a bunch of other things.
