That first “Exception: 4” for U7 seems legit.
The error is about the distance between the pads, and with a footprint with a pitch of 0.4mm there is not much room left if your PCB manufacturer wants a clearance of 0.2mm.
The way to fix the clearance issue is to modify the footprint itself to use smaller pads. Or use another footprint with a bigger pitch.
The screenshot of L4-U14 looks like your PCB manufacturer substituted their own footprint for L4, and it does not even fit on the pads on the PCB.
And that makes me suspicious about the other footprints.
The white line in the screenshot of the KiCad footprint of J8 looks like it’s the courtyard. Is that correct?
And where does the red line come from that your PCB manufacturer drew around J8. Is there anything in the KiCad file that resembles those lines?
File-Board Setup-Design Rules-Net Classes.
You can specify Clearance as 0.2mm and DRC will give you an error whenever clearance between any cooper elements belonging to different nets will be closer than 0.2mm.
If they require 0.25mm for BGA pads then you should have at least such pads in your footprint.
In previous century I ordered PCBs where minimum clearance was 6 mils (0.1524mm). That manufacturer (our local) now offers clearance of 4mils (0.1016mm). So one of solutions can be to change the PCB manufacturer.
For me it looks that someone defined J8 connector footprint to allow to use just pin-headers or socket with bigger plastic case. If you use only pin-header then the source of problem is: where from the PCB manufacturer sees that red rectangle - he should not get it among gerbers.
You should know what are the real dimensions of L4. If it really occupies such big space as we can see that it really collides with U14. If not - then once more - where from PCB manufacturer get that big rectangle. You probably send him the file he should never even see. If he will not see it he will not have a problem with it. Just send only files needed.
After your comments I discuss the same with manufacturer and clear that the red line shows outline of component that they determined from MPN.
Actually I have made wrong footprint design. They highlighted the same.
In J2 I have taken wrong dimensions.
But I have still ambiguity in L2 and L4 with MPN(“DFE18SANR24MG0L”) and I have taken “L_0603_1608Metric” footprint from kicad library, whose dimension is 2.96mm x 1.46mm , dont know why it is so ? for a 1608 package it must be 1.6mm x 0.8mm, is I am missing something here
Have you ever seen PCB with elements assembled on it?
Do you suppose that elements are placed at PCB one touching the next one and so on?
In footprints you have the exact element dimensions at F.Fab layer (here 1.6x0.8) and rectangle with some margin at F.CrtYd layer (here 2.96x1.46). When you place elements so that rectangles at F.CrtYd don’t overlap you can be sure the PCB can be assembled.
This might however make soldering a problem. So a possibly better option is to either switch to a component that has a larger package (for example a DFN or QFN variant of the same component if available).
Or change to a PCB manufacturer that can deal with the requirements of BGAs with such a small pitch.
I looked up that MPN on OctoPart and got a datasheet. Here is a screen capture of part of the first page: (Sorry about the scaling, I didn’t want to make the screenshot too large. I can just make out the dimension text.)
Looks to me that the part takes a 1608M footprint and the body of the part wouldn’t extend past the footprint pads. The screenshot you give of Exception 3 appears to show a larger expected component body (thick-line rectangle) and differently shaped suggested pads (thinner, concentric rectangles). There is probably a disconnect somewhere between what part you expect to use there vs. what the manufacturer expects to use there.
Also, the 2.96mm x 1.46mm dimensions that you mention I see on the L_603_1608Metric footprint as the dimensions of the courtyard for that footprint. (Basically the clearance around the part that you should avoid putting other components in to improve manufacturability.) The actual part is 1.6mm x 0.8mm, but the pads necessarily have to extend beyond that size to allow for proper solder fillet formation during soldering. This KiCad footprint looks (to me) to be automatically generated so I would expect it to conform to IPC standards for reliable manufacturing (knowing what little I know about of the KiCad Librarians team’s practices). But, it is best practice with any 3rd party (to you or your organization) footprint to “trust but verify”, including KiCad’s supplied libraries.
Similar issue (as already mentioned) about your pin header. The default pin header footprint in KiCad only provides a courtyard for a bare, right angle pin header which fits in your design next to J12. But the expected body size in the exception screenshot appears to be a shrouded pin header which would not fit. Check that both you and your manufacturer agree on the actual part that you intend to use for J8. I see you have already acknowledged that you “took the wrong dimensions”. If you are using a shrouded pin header, recognize that not all shrouded pin headers are the same. There are several 2x5 shrouded pin headers across multiple libraries. I filtered on “2x05 horizontal” and came up with 34 footprints across 9 libraries outside the 7 different sized Connector_PinHeader... libraries. (I’m referencing the libraries that shipped with 5.1.10). Maybe one of those 34 footprints is for the part you plan on using at J8 or is close enough. Or, maybe you will need to create your own footprint.
While checking on L4 and J8, you might just want to double check your other components to make sure that you used the correct footprint for the actual physical part that you plan on using. Yes, this will probably take several hours or days, but that sure beats loosing several weeks turnaround and wasted materials on another error that you could have caught before hand.