In Eagle I run the ERC which tells me if the board differs from the schematic. Is there a KiCad tool that performs a consistency check in a similar fashion ?
That would be a good feature.
I think the closest is if you do a netlist import, and then run DRC.
Do a dry run of netlist import?
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Just out of curiosity… How did the layout manage to become different to the schematic that you would need an automated check for?
As I understand it the schematic is the ‘master’ and the layout the ‘slave’, if the layout differs from the schematic it must have been on purpose, no?
What do I miss?
What’s the use case?
Thanks for enlightening.
I think that ERC in Eagle is exactly the same as in Kicad… DRC is (also in both) checking consistency between schematics and board. ERC does not know anything about the board…
I assume this more than likely scenario:
Someone changes in eeschema the reference of a resistor from R3 to R4. Then generate netlist, read it with pcbnew. The import log tells me that a resistor R4 is now being added. But it does not tell me that R3 does not exist any more. It just adds another resistor to the board.
Please find the dummy (test) project at
http://www.blunk-electronic.de/download/kicad/i2c-parport.zip
Thanks for your help !
This behavior depend on some options in netlist reader window.
If you change reference from R3 to R4 on schematic and generate new netlist, the netlist reader from PCB only inform you about this change if the Footprint selection via Timestamp will be used. Any new footprint will not be added, the reference will also be changed in your PCB. See log:
Changing component "R3:/56ABDDD2/56D8A581" reference to "R4".
Otherwise, if you keep default Footprint selection via Reference the netlist reader insert new footprint. Just like in situation described above. But, if you change another option called Extra Footprints to Delete, then R4 will be added and R3 will be removed. See log:
Adding new component "R4:/56ABDDD2/56D8A581" footprint "Resistors_SMD:R_0805".
...
Removing unused component "R3:/56ABDDD2/56D8A581".
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Thanks ! The Timestamp thing got me what I wanted. 
The usefulness goes beyond annotating components with reference designations. For some people (or some organizations) it’s an occasional by-product of the process of human creativity. For example, as you develop a board layout it becomes obvious that two transistors in separate SOT23 packages actually fit more efficiently than electrically equivalent parts housed in a single 8-pin package. Or somebody in Purchasing, Material Control, or Production Engineering decrees that all resistors will be 0603 sted 0805. Or the circuit designer refines his calculations and decides that a particular signal needs additional buffering, and there just happens to be an uncommitted line driver in a component on the board. Or availability problems force a part that’s not yet incorporated in the library to be substituted for a part specified in the schematic.
Some PCB layout tools allow you to add or delete both footprints and connections during layout, though KiCAD doesn’t really support that capability. At any rate you end up with a board layout that is not 100% correlated with the schematic. Of course they eventually WILL be correlated but it’s annoying, inefficient, and often error-prone to switch back and forth from PCB layout, to schematic, every time one of these changes comes up. (Yes, I know this is a very individual characteristic based on how each of our brains, thought processes, and creativity are “wired”. That’s a discussion for a different thread.)
Until all the changes flow back and forth through netlist and CvPCB files it would be convenient to have at least an informal tally of the differences - to verify that the intentional differences have all been incorporated, and that no unintended differences are present. Forum member @cioma has the best current answer: “Do a dry run of netlist import?”. That will flag all differences and the user must straighten out the intentional differences from the unintended, but it would be nice to have a tool allowing the layout guy (or gal) to flag a discrepancy and tell PCBNew “Yeah, this is not consistent with the netlist but trust me - this is what I really want to do and it will all get resolved in the future. Ignore this when you do DRC’s.”.
Dale
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Dale,
Just out of curiosity… How did the layout manage to become different to
the schematic that you would need an automated check for?
Very easy. Assume the average user who just hoovers the cursor over a part in the board drawing, who then presses DEL. She/he might or might not have a clear intention to do so. The part gets removed from the design and nothing prevents or even warns the user.
That’s in KiCAD BZR6907, still not gotten around to install the latest nightlies, but don’t think behavior has changed…
I can sign up on that one. Is there a buglist/wish for that?