Connecting multiple Power Outputs without ERC error

Schematic
1

Connecting multiple Power Outputs results in the ERC error “Error: Pins of type Power output and Power output are connected”:

power_outputs
power_outputs1513×303 26 KB

I understand why this is happening and it usually makes sense. But I add additional footprints that are not supposed to be placed, in case parts become unavailable at some point in the future.

There are a few other older posts on the forum with the same question and the solution seems to be to copy the symbol to a custom library and edit the pin type to passive. That might solve the issue, but it is quite cumbersome and feels very wrong from a design point of view.

Is there a way to tell KiCAD to allow this? Or to ignore some components?

What I currently do is to ignore the ERC warnings but that seems more like a workaround than a good solution. What’s the recommended way to solve this?

Application: KiCad Schematic Editor

Version: 6.0.6+dfsg-1~bpo11+1, release build

Libraries:
	wxWidgets 3.0.5
	libcurl/7.74.0 OpenSSL/1.1.1n zlib/1.2.11 brotli/1.0.9 libidn2/2.3.0 libpsl/0.21.0 (+libidn2/2.3.0) libssh2/1.9.0 nghttp2/1.43.0 librtmp/2.3

Platform: Linux 5.10.0-11-amd64 x86_64, 64 bit, Little endian, wxGTK, lightdm-xsession, x11

Build Info:
	Date: Jul  1 2022 17:47:41
	wxWidgets: 3.0.5 (wchar_t,wx containers,compatible with 2.8) GTK+ 3.24
	Boost: 1.74.0
	OCC: 7.5.1
	Curl: 7.74.0
	ngspice: 34
	Compiler: GCC 10.2.1 with C++ ABI 1014

Build settings:
	KICAD_USE_OCC=ON
	KICAD_SPICE=ON
2

You can use a net-tie between the outputs of the two chips.

It is not a very elegant solution.

Or create a symbol and an footprint with both the footprint and the courtyard of the largest.
And fix the various layers of the impression.
In the event that the two footprints are not the same and consequently the second solution is the best.

There is also another possibility to not modify the impression, find an equivalent component with the same footprint.

3

You can also place a 0 Ohm resistor in between the two signals.

4

The solution with prepending the “#” sounds promising, but I can’t get it to work. It behaves as the name just starts with “#”.

Using a net-tie sounds like an ok solution, but I’m hesitant to put extra, completely unnecessary footprints on the board just to suppress an ERC error. Is there a way to use a net-tie without specifying a footprint, so a regular track is used rather than a 0Ω?

5

I did something similar, I had footprints for different packages of the same voltage regulator. I just ignored the error and wrote a note on the schematic that only one is to be installed. Since I’m the only person using my design I’m unlikely to install both components. :wink:

6

At the risk of being spurned/ostracized/excommunicated/banished, I too must confess to, on occasions, just ignoring ERC warnings.

I know what I’m doing (at least that is what I think) so the computer program can just cope with my behavior and decisions. :slightly_smiling_face:

7

You can use “exclude this violation” in the ERC dialog, using the context menu on a message item.

IMO this whole power check in the ERC is a bit flawed. It’s just too fragile, it works as wanted only in some cases. It requires certain kinds of symbols for input/output and they must be connected directly. As we have seen, it can’t cope automatically with any special situations, and it doesn’t understand for example diodes after power output pins.

1 Like
8

Another way to suppress the warning is to change the output type of one of the voltage regulators to “passive”. To do this:

  1. Hover over the schematic symbol in the Schematic Editor.
  2. Press Ctrl + e to load the symbol in the symbol editor.
  3. Edit the pin properties of the offending output.
  4. Close the Symbol Editor. (It then asks you whether you want to save the changes into the schematic).
9

If looking at the two symbols, the footprint is not the same for the two chips as a result the fingerprints must either be superimposed in some way or separated and add gimmicks to avoid errors or ignore them once the pcb is completed.
Altium-style variants should be managed for a clean workflow.

10

I like to stack my resistors nice & close, and get a “Courtyards overlap” DRC error , and yeah, I just ignore the errors. Again, the PCB is just for me…

11

You could reduce the courtyard in your personal library if it is too large for your application.

12

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