I have analog and digital grounds in my design. I want to connect those by short schematic symbol
(or solderjumer), but I don’t want that solderjumper to appear in the netlist I extract from the schematic.
So in the netlist I dont want to see presence of ‘shorting’ components.
Is it possible with KiCAD 5.1 ?
Have a look at “Net Ties”. There are a variety of options (2way, 3 way etc) and appropriate footprints.
Thank you, but NetTie doesn’t work for my needs.
With the NetTie you have a regular symbol with pins #1 and #2, but in the Footprint those pins are connected together. Then in the board digital and analog ground become one net (because of Footprint), but in the schematic they are not.
If you extract netlist from a schematic then you will get NetTie component present in the netlist and pins #1 and #2 connected in the netlist.
To me it means that the netlist extracted from schematic creates a confusion.
I’m looking for a solution where the netlist extracted from schematic doesn’t have components that I don’t want to be there.
Other systems have a way to do that.
Does KiCAD have a way to mark a component on a page so it is ignored in the netlist ?
Not with 5.1.x and equally not with 5.99
Although the netlist becomes less significant in 5.99
What problem are you attempting to solve? Net-ties are the typical way of dealing joining dissimilar named nets with different constraints
Also… Split analogue and digital grounds is the old method of dealing with the problem. A more logical placement mitigates the problem
https://resources.altium.com/p/splitting-planes-good-bad-and-ugly
To make things easier, we can readily debunk all of
the foregoing and say they are not true. But, perhaps one of the most important takeaways is that you should NEVER, EVER cut a ground plane. If you do, you will destroy the integrity of your PDS.
Simply put, this is not possible. The concept of the netlist is what allows a separation between the two “ground” nets. So, the desire to have two different “grounds” but only one in the netlist does not make sense.
3 Likes
You are not answering the question.
I’m ok with 2 different nets in the netlist.
I’m asking whether it is possible to mark some component so it is not output into the netlist.
Many schematic systems do allow it, because it is a useful capability to have.
If you at schematic will have 2 separate grounds and something connecting them then I see 2 possibilities for netlist:
- they both become one net,
- they stay separate nets but there is element connecting them.
According to my imagination in any other case the netlist will be not in accordance with the schematic. I don’t understand the need for lying netlist. Accepting something like that is the short way to get PCB wrongly designed. I suppose others here think like me.
If you don’t accept any of these 2 possibilities than it would be useful if you clearly explain what you really need and why. The best would be with simple schematic and how you expect netlist should look like (how that simple schematic is represented in netlist).
If you want two separate grounds and want something at schematic that looks like connecting them together but really not connecting them (you not want it in netlist so you not want the grounds to be connected) then you can just use graphic at schematic. You can also define symbol having no pins so it will not connect anything.
You can export the net list in other formats - I believe that Orcad is a possibility. Perhaps that will allow you to achieve what you need as you say that other programs allow this? Otherwise, not really sure that I understand - the nets are either separate or joined - not both.
KiCad does not have a system to allow you to mark two separate nets as connected (a net tie) without there being a net tie component in the netlist. This is how KiCad’s netlist format works. Other programs may be different.
We plan to support other types of net tie in the future, however “excluding parts from the netlist” is not an explicit goal of this work (it just might happen as a side effect). You can exclude parts from transferring to the PCB, but not if these parts are supposed to connect two nets together.
There are a
Schematic components that are prepended with a hash sign in the RefDes (Reference) are not added to the PCB (And I think also excluded from the BOM.
Power symbols are pretty simple in KiCad, although not really straight forward.
Power symbols have a pin (Which must be stet to “Power Input”) and the name of the pin is treated as a global label.
With this in mind it is quite easy to make several different GND symbols that connect to the same Net. The “GND” text in the GND symbol is just that. It is text. The actual pin (from which the label is derived) is hidden. Just open the GND symbol in the Schematic Symbol Editor.
This can get a bit confusing if you’re not designing the PCB yourself. Even if you design the PCB yourself, make some notes that the visually different symbols actually are the same net, and separation of GND current paths is totally up to the PCB designer.
1 Like
the OP still hasn’t answered the question:
What problem are you attempting to solve? Net-ties are the typical way of dealing joining dissimilar named nets with different constraints
Why don’t you want it appearing in the Netlist? its one thing to not want it appearing in the BOM (and thus doing some tidying up of the BOM), but the netlist? the netlist is used by EESCHEMA and PCBNew to describe interconnectivity and to join to dissimilar nets a net-tie item is used and thus must be describe in the netlist.
Yes other programs might have other methods but Kicad does not so, why don’t you want it appearing in the netlist? what are you doing with the netlist directly that is causing problems?
I don’t like net-ties appearing in the BOM, I don’t like net-ties in PCBnew (although necessary evil) but I don’t care about it at netlist level
This smells like an X-Y problem
2 Likes
It isn’t an answer to your question, but i would advice you not to split grounds. Splitting grounds cause more EMC problems.
It is better to separate the signals types in different regions, means one region where you route the analog tracks and a other region where you route the digital tracks. And leave a gap between this regions (the ground planes should not have a gap, only the signals).
1 Like
@kicad234, this seems to be the correct answer, but take this hack at your own risk, it will look like a mess for other person than you. For instance, half of your same-named gnd nets will not be highlighted by “highlight net” tool.
But I agree to all posters here, it is a mystery what is the problem OP is trying to solve…
This topic was automatically closed 90 days after the last reply. New replies are no longer allowed.