Confusion of netlist in pcbnew, spagetti

Hi, Im back :slight_smile: after a year or so absence.

I left my designs in a bad state: i have a some kind of confusion between schematics
and the PCB I made. In PCBnew, when applying the netlist, I get spagetti, although the card
previously had all vias in place. I think I somehow introduced a new component (or fotprint or something) that made some matching ascew so that the wrong compontens are assumed somehow.

Any clues, probably I have to do some handywork directly in one of the files of the project
but which one, and where/what should i look for.

Much appreciated, Georg (btw I tried to search an entry for this but didnt, but the problem must be quite common ?)

It sounds a bit like you have re-annotated the schematic. You could try to re import the netlist with “by timestamp” instead of “by reference”

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ok will try that, but I would much like to find some text describing the tags and connections between the file formats of eg. .net and .pcb ?

eureka; it seems to work at first glance (if there actually was an import, not much happend :slight_smile: so now I will see if I can make “real” changes in the schematics and get sane implications in the pcbnew. many thanks (hoping that this was it)

If I now save the project, can I switch back to importing by ref (or is that unecessary)

And of cause THANKS

/g

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