Confirming via behavior

I recently started using KiCad versus a different package and trying to adjust on using vias and filled planes in KiCad-style.

In my prior package, for every via and every through-hole (i.e., as part of a part), I could select if that hole was connected to each PCB layer, and also the type of connection, i.e. full or thermal. So I could place the vias first, then connect the traces and assign which layers each via was connected to.

In KiCad, it seems a lot of this is automated, but I want to confirm I am not missing anything.

So, is it true that KiCad links each via and through-hole pin to every copper layer that is on the same network?

In other words, in a 4 layer board, if I lay down 4 planes overlapping each other and assign them to the same net, if I place a via and assign the via to the same net, then the via will be connected to all layers?

I have never designed 4 layer PCBs but I would not expect via going through the same net zone being not connected to it.

It seems that way from my limited testing.

The zone settings change the THT thermal connections, or not, to the different layers.

All of the copper connections can be seen in the 3D viewer. Turn the different layer visibility in PcbNew to what you want to see in the 3D viewer. It may help to turn off the board edges and soldermask visibility in the 3D viewer preferences.

Thanks - this all makes sense but wanted to confirm in a way other than ordering a PCB and seeing what it’s like.

Regarding the 3D view, I tried that already, great feature by the way, but I have a hard time figuring out what is plating and what is not. However, as I have been working with the system more, I can clearly see vias that are not connected to a plane in a layer as the pour creates an empty circle around them.

I was a bit bummed about losing the ability to explicitly specify the via-layer connections but as I get used to this, it’s probably a better way to do it.

Not so sure you really need to be able to do this, but I think you can. Fill zones can have Fill zones in them with different priority levels.

Oh, and move the THT parts and VIA near the edge of the board and only turn on one copper layer at a time when using the 3D viewer.

just curious, why faff around with the 3d viewer instead of just selecting that copper layer in pcbnew (or gerbview to double check?)

I think a layer tht pad (and via) layer stackup manager is planned for some future release. Until this point one can sadly not specify different shapes (annular sizes) on different layers. (There is then no way to specify having no anular on a layer that is not needed and therefore not really a increase in space for traces or zones on layers without connection)

Regarding connection: well zones define how something connects to them. There is no way to choose thermals for vias (only for tht and or smd pads) as it is not seen as something that is needed. After all thermals are needed to reduce thermal flow for easier soldering and vias have nothing soldered to them.

Same reason for printing out Word documents to proof-read on paper. The brain tends to not see them both the same way.

And, one element is 2D and the other element is 3D.

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