If IC has VCC/GND as adjacent pins then connecting to 0201 can be very short, but tracks to 0805 have to be longer. You can say that internal connection (in IC) from chip to case pins are longer so external don’t cares, but internal are close to each other and paralel - they couple together and you can look at them as a HF common mode choke. External connections are not paralel.
Agreed, In those cases where Vcc and Vdd are adjacent (or even close).
Sorry for the delayed response but no, I don’t have a “howto”. But in every application note or article about bypass capacitors or layout considerations, I remember “Via-Cap-IC” and I believe(!) you can keep your supply “clean” this way. I’ve also made simulations about bypass capacitors and even multiple in parallel and I can say, the ripple at the IC pin may be heavy, even after a 2mm track (what’s roughly 2nH of inductance), and this would couple into your power planes. My way is simply “use the smallest type you can handle with the biggest capacitance”. Multiple in parallel create tank cirquits that can be difficult to plan. Keep it short and simple… 
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Actually, we do it in our manufacturing process for many of our customers. Passives smaller than 1210 will happily stay soldered on the underside of the PCB as it goes through the reflow a second time so as to solder the newly placed top side components.
The temperature on the underside of the PCB in the reflow process isn’t hot enough to cause the solder to melt.
The cost comes in having a second paste screen, and having to basically paste/place each board twice.
If you subsequently need to have the board go through the wave soldering process with bottom side SMT parts, life starts to get complicated! Unless of course you have a selective soldering machine
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If you have a selective soldering machine, then it would be extremely unlikely you would do wave soldering on the same PCB.
https://www.youtube.com/results?search_query=selective+soldering
I understand this selective soldering machine as selective wave soldering machine so using it means you do wave soldering. But I’m not sure if my understanding is well. Two years ago I didn’t know such machines exists.
The aim of the short traces between the capacitor and the IC is to keep the inductance of this trace as low as possible. The inductance is proportional to the area between the traces. The length has a great effect on the size of the area (that is logical), but the length is not everything. The area is shown in yellow. For all examples I use a QFP package with 0.5 mm pitch.
The way in which the traces are routed also has an effect.
The example on the left may be the most common way. The length of the eample on the left and the middle is the same, but the left example is better due to the smaller area. The length of the example on the right is the longest, but the area is the smallest and also the inductance. Of course, for 0603 it doesn’t make a difference, but for 2512 (maybe a shunt) it will. For 0603 I use the way shown in the left example for myself.
Now we will compare 0603 to 0402.
There is also no big difference. For DFN/QFN it will be an advantage, but even then, the question is whether it is relevant at all. In Most cases it isn’t, especially for circuits designed by people who are not so familiar with this context.
And of course you have to route the traces from the source so the capacitor and then to the IC. The following equivalent circuit illustrates the difference.
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Agree. You either selective solder, or wave solder. I wasn’t suggesting (and not sure how you read into my response that I was) you’d do both.
But if you do bottom side SMT and need to subsequently solder through hole components, and only have access to a wave soldering mạchỉne, then you need to glue the bottom side components in place and then have a special agitated wave.
You also need to take special care with footprint design when putting SMT components through a wave soldering process otherwise you can get bridging.
A selective soldering mạchine eliminates these complexities and makes it easier to mix THP and bottom side SMT in the one design
Hmmm. That’s not my experience with JLCPCB. I’ve had to rework 0402 resistor arrays on about 50% my boards due to solder bridges between pins!
Hello, thanks for the response. So if I am trying to put the bypass capacitors on the different sides of the board, is it possible to put one capacitor on the one side and another on the other but with exactly the same place, and connect them direct with vias ?
Sure, that is possible, but do you really want to do that?
Putting decoupling capacitors so close together does not have much benefit. You could as well have used a capacitor with a bigger capacitance (but beware of parasitic properites, which sort of scale with physical capacitor size).
Some other things to consider:
- Vials though pads is bad practice for production ( They suck up the fixed / limited amount of solder paste) (But for home soldering of hobby projects it does not matter much).
- For production, there is a cost penalty if you have (SMT) footprints on both sides of the PCB.
Yes, because my supervisor asked me to put part of the capacitors on the other side of the PCB so generally the capacitors could be closer to the chips(I told him that there won’t be much benifit,but he insist me to do so), so the first thing come to my mind is that to put two capacitors on the same place of each side of the pcb and connected them directly with vias.
By replace with a bigger capacitors:
Did you mean that for example I can replace four 100nF capacitors with one 400nF capacitor ?
Lots of good info out there on the “Net” . . .
I don’t know the whole picture. Do the ICs are on both PCB sides or not?
If yes then I agree that among ICs at other side it is rationale to place some capacitors to be closer to those ICs.
But if ICs are only at one side the capacitors at other side will not be closer to ICs itself as the PCB has its own, not zero, thickness. Practically the only effect will be to make PCB assembly more costly.
If IC has 4 supply pins (typically one at each side) and you place 100nF as close as possible to each such power pin then replacing them with one 400nF is stupid.
If from any reason you have 4 100nF placed in paralel just touching each other than replacing them with one 400nF in most cases also gives you nothing except new value to be used during assembly (costs). You should better replace them with one 100nF instead (as in other places at PCB you probably also have these 100nF).
If more capacitance is needed than instead of using 400nF I would use 1uF or more.
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0603 is fine, try and find capacitor space on the top layer…
connect vias to caps then caps to IC pins.
on bottom layer, you have via inductance between top sided IC and the cap. less good.
Yes, 4 x 100nF caps for four power supply pins. If a device has separate power pins, then it wants separate bypass caps, but there are exceptions, and when using planes and BGAs, this may not be feasible. Once rise times get fast, it’s a different game, and you rely on the interplane capacitance to do the immediate bypass work.
multiple vias on a single pad next to each other doesnt help via inductance. better to space them at least a board thickness apart. I would suggest NOT putting vias in pads for components. This is just downright design lazy unless you have 10 layers and no room on top or anywhere. Vias in pad is for 0.5mm BGA.
if you really must get the inductance down, position the vias next to eachother (different pads) like this .
this way the currents in the vias will have a chance of cancelling each other.: (opposing mag fields)
There should be solder mask between the VIA and the component pads (or tented vias)
Glen, would you mind expanding on why you would discourage via in pad for bypass caps etc? I’m new to PCB design and was under impression most avoid via in pad due to cost only.
- it adds cost. the vias must be copper plugged
- this pulls heat of the the pads which creates more difficult soldering conditions. Your soldering reflow curves process must be customized.
- For 99.9% of PCBs in the world , via in pad will not made any measurable or useful difference in performance .
- It’s all about rise times, unless you are designing with high current hundreds of MHz FPGA / memory designs, it wont make any difference if the vias feeding the capacitor pad are 5mm away from the paid. nothing.
- what I have shown in the image above is abotu as extreme as you need to get,
- The only valid condition I see to choose via-in pad would be on the back side of a BGA, where the BGA balls and capacitors have the same pitch. Then, yes, using via in pad might be the only option for you.
Most people get carried away … If you do the math and the sums, you’ll find in most cases, via-in-pad will make no difference.
Via in pad should be driven by a need - that is where is is no space for vias or traces. - on the back of an FPGA or BGA microprocessor or memory.
I do not use any VIA in pad on any of my designs, except for 0.5mm BGA where there is no room for vias between pads without exotic methods.
Otherwise, vias should be connected with a trace and not stuck on the ends of pads.
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Hello guys, I find out that if I want the bypass capacitors to be really close to the pins, one solution is to put the capacitor on the backside, and excatly under the pin which it should be connected (the pin is on another layer), and connect them directly with vias in pad (or capped vias, plugged vias). I have found something on youtube shows that it might be promising :https://www.youtube.com/watch?v=-L-0CkH3aEk
And also find a manufactory which could provide this technology:https://www.aetzwerk.de/
according to their site:
English translation (if needed):
''Here, the vias are completely exposed from the solder resist and a non-conductive paste is pressed into the drill holes. The pad is produced by electroplating. The via drill hole is no longer visible on the outer layer. This process is suitable for via drill holes from 0.2 to 0.4 mm.
Via in pad technology offers several advantages:
BGA pads can be used as via pads at the same time.
Realisation of stacked blind vias.
Improved heat dissipation. ‘’
So is this a reasonable solution ?
And if yes, can I just set this connection by placeing a via directly on the BGA pad:
switch to another layers and move the capacitors so its pads could cover the vias ? :
Thanks 
try to avoid that. If possible, offset between backside vias and use traces.
Unless this is 0.5mm BGA, you should be using fanout, not via in pad.
Hopefully, you are using power planes, you can put the capacitors outside the BGA footprint within a rise time distance of the pins and it will do the same job… no need to be on the back of the package…
You might get a shock on price, depending on your expectation, it would be 0.2mm drill… and ENIG is a must to ensure flatness
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