A complex Edge.Cuts layer may require many lines and arcs. Often a Margin layer is needed to match the Edge.Cuts to allow a correctly bounded copper pour like in this image:
With a DXF double import: One to Edge.Cuts, another to Margin. However, if a DXF is not the source of the board outline, or is lost, or requires lots of tidying up etc., then I might try:
Graphically via two PCBNew instances:
In high contrast mode, select and copy applicable Edge.Cuts artwork
Open a new PCBNew window and paste.
Edit > Move and Swap Layers.
Copy+paste back into projectās PCBNew window. Or,
Kicad script:
In high contrast mode, select applicable Edge.Cuts artwork.
Run this script to copy selected drawing segments to Margin:
import pcbnew
board = pcbnew.GetBoard()
for drw in board.GetDrawings():
if drw.IsSelected():
drwCpy = pcbnew.DRAWSEGMENT(board)
board.Add(drwCpy)
drwCpy.SetStart(drw.GetStart())
drwCpy.SetEnd(drw.GetEnd())
drwCpy.SetWidth(drw.GetWidth())
drwCpy.SetAngle(drw.GetAngle())
drwCpy.SetArcStart(drw.GetArcStart())
drwCpy.SetShape(drw.GetShape())
drwCpy.SetLayer(pcbnew.Margin)
Because of a bug in Kicad I then need switch to legacy canvas (F9), then back to modern canvas (F11) to refresh the artwork.
All of these approaches can be pretty cumbersome, so Iām wondering if anybody has discovered a better way?
In Altium Designer for example, I am able to copy+paste, then use the PCB Inspector tool to switch the layer of any selected items.
Sounds here like Kicad really needs a Clearance to PCB edge option ?
Other CAD pgms have more options in their clearance rules.
? I can create a polygon on Edge, and move to Margin by simple select, layer change ?
I canāt change it to F.Cu, or change a F.Cu layer to non-copper, but thatās Kicad trying to protect users.
You can easily edit the design file.
Margin seems to have no effect on any pour, so if you do want a Fill area to have an edge clearance not the same as other clearances, you will need a second polygon, shrunk manually, best done via DXF import from CAD pgms that can easily manage shrink ?
? I can create a polygon on Edge, and move to Margin by simple select, layer change ?
I canāt change it to F.Cu, or change a F.Cu layer to non-copper, but thatās Kicad trying to protect users.
You can easily edit the design file.
Do you mean a āfilled zoneā in Kicad vernacular? Iām aware you can change the layer of a zone very easily, but then you have the issue of creating a complex zone outline. You canāt easily do this *without some hackery IFAIK, so the problem remains. As for individual lines/arcs, these can be changed individually, but not in bulk selection.
I just tested the layer-change detail.
Margin seems to have no effect on any pour, so if you do want a Fill area to have an edge clearance not the same as other clearances, you will need a second polygon, shrunk manually, best done via DXF import from CAD pgms that can easily manage shrink ?
Interesting. I was so sure it did have an effect (maybe that was in V4??). It seems a the filled zone (e.g. in my image above) is using the edge cuts as a perimeter. I donāt think this is necessarily the correct approach, but makes things easier in most cases.
In AD I would define a keepout, usually to be a minimally modified copy of the edge. This would be the copper pour edge. Sometimes you might want it to run over the edge, hence why I donāt know that itās the correct approach to assume the PCB edge will always define the copper pour marginā¦
I thought the kludge to enforce a āClearance to PCB edgeā in KiCad was to understand that the board will be milled to the centerline of the board outline on the Edge.Cuts layer, but the copper-to-copper clearance settings for the pour will treat the Edge.Cuts lines as copper traces and enforce clearance to the edge of the line. Thus if you want a larger copper-to-edge clearance than the normal copper-to-copper you make your board outline on the Edge.Cuts layer as wide as twice the difference between the two clearances.
For example, if you want 10mil clearance copper-to-copper, but also want 15mil copper-to-edge clearance. The difference is 5mil, so you would make the lines for the board outline on Edge.Cuts to be 10mil wide. This would also enforce DRC to keep traces at least 15mil from the centerline of the board outline.
See above also - you can use the width-is-used effect to skip the shrink step, if you want a larger PCB clearance.
Of course a fat Edge.cuts line looks strange, so you might want a finer copy on another layer to give to the FAB - but thatās now a simple copy, as the line width manages the shrink.
If you wanted a special case PCB edge (as in a edge connector) then I think you need to use (eg) margins as a PCB fab indication, and use Edge.Cuts (line edge used) as the pour-limit control.
Yes, KiCad lacks finesse in many āgroupā operations.
You cannot for example, ^Click to select multiple entities.
You can mouse-box select a number of lines, and duplicate works on that as a whole, but you cannot then change layer on that selected group. You must use a script, or deselect, and change each segment, one at a time.
Also, Zones behave like polylines, but normal drawing lines do not, so there is no segment-drag.
I think polyline support is coming, so you will be able to drag a segment, and extend the connecting lines ?
For traces and vias it is possible to open the properties dialog for multi selection in v5. (so you can change the layer and trace width of all selected traces at once) Sadly not for anything else.
I donāt think you need to do anything more than define the fill-zone as a rectangle circumscribing the board outline, and fill it. The algorithm places copper up to the board outline, less the āclearanceā parameter. You may have to be careful that the outline on the Edge.Cuts layer is a strictly closed contour.
The clever trick of adjusting the board-edge clearance isnāt too difficult in practice. Select everything on the Edge.Cuts layer, change the line width, do the fill, then re-set the line width if necessary.
I am NOT a programmer but my superannuated brain (which learned āFortran IIā over half a century ago) wonders if this feature could be easily implemented by defining the Edge.Cut as a special kind of Net Class, with an associated Clearance parameter just like any other Net Class.
Yes, that seems a good approach, as that structure is already there.
You can have a net entry with 0 connections, and a net called Edge.Cuts is valid.
It just needs to be āappliedā to the edge cut lines during fill.
It could be applied to traces or footprints in general, and checked during DRC. In years past, board fabricators imposed a requirement for edge clearance, just like requirements for trace spacing - except the required edge clearance was often larger than trace spacing. In those days the edge clearance was a design rule just like trace width or spacing, and something to be checked by DRC. In recent times they are more tolerant of things like edge contacts, plated-through castellations, etc, so the āruleā is much less definitive. Even so, I think thereās value to defining the Edge Cut as a kind of net, with clearance requirements like any other net.
